[coreboot-gerrit] Change in coreboot[master]: mb/scaleway/tagada: Add Scalway Tagada Board
Julien Viard de Galbert (Code Review)
gerrit at coreboot.org
Thu Feb 15 17:37:26 CET 2018
Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/23782
Change subject: mb/scaleway/tagada: Add Scalway Tagada Board
......................................................................
mb/scaleway/tagada: Add Scalway Tagada Board
Change-Id: Id4ecb760b9ab07ab168b252542dcaaea4636d655
Signed-off-by: Julien Viard de Galbert <jviarddegalbert at online.net>
---
A src/mainboard/scaleway/Kconfig
A src/mainboard/scaleway/Kconfig.name
A src/mainboard/scaleway/tagada/Kconfig
A src/mainboard/scaleway/tagada/Kconfig.name
A src/mainboard/scaleway/tagada/Makefile.inc
A src/mainboard/scaleway/tagada/acpi/mainboard.asl
A src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl
A src/mainboard/scaleway/tagada/acpi/platform.asl
A src/mainboard/scaleway/tagada/acpi/thermal.asl
A src/mainboard/scaleway/tagada/acpi_tables.c
A src/mainboard/scaleway/tagada/board_info.txt
A src/mainboard/scaleway/tagada/devicetree.cb
A src/mainboard/scaleway/tagada/dsdt.asl
A src/mainboard/scaleway/tagada/fadt.c
A src/mainboard/scaleway/tagada/gpio.h
A src/mainboard/scaleway/tagada/hsio.c
A src/mainboard/scaleway/tagada/hsio.h
A src/mainboard/scaleway/tagada/ramstage.c
A src/mainboard/scaleway/tagada/romstage.c
19 files changed, 2,008 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/23782/1
diff --git a/src/mainboard/scaleway/Kconfig b/src/mainboard/scaleway/Kconfig
new file mode 100644
index 0000000..2af3e29
--- /dev/null
+++ b/src/mainboard/scaleway/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_SCALEWAY
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/scaleway/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/scaleway/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Scaleway"
+
+endif # VENDOR_SCALEWAY
diff --git a/src/mainboard/scaleway/Kconfig.name b/src/mainboard/scaleway/Kconfig.name
new file mode 100644
index 0000000..abbc9e7
--- /dev/null
+++ b/src/mainboard/scaleway/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_SCALEWAY
+ bool "Scaleway"
diff --git a/src/mainboard/scaleway/tagada/Kconfig b/src/mainboard/scaleway/tagada/Kconfig
new file mode 100644
index 0000000..53c1f6d
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/Kconfig
@@ -0,0 +1,36 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 - 2017 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+if BOARD_SCALEWAY_TAGADA
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SOC_INTEL_DENVERTON_NS
+ select BOARD_ROMSIZE_KB_16384
+ select HAVE_ACPI_TABLES
+
+config MAINBOARD_DIR
+ string
+ default scaleway/tagada
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "TAGADA"
+
+config MAINBOARD_VENDOR
+ string
+ default "Scaleway"
+
+endif # BOARD_SCALEWAY_TAGADA
diff --git a/src/mainboard/scaleway/tagada/Kconfig.name b/src/mainboard/scaleway/tagada/Kconfig.name
new file mode 100644
index 0000000..67e5e0a
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_SCALEWAY_TAGADA
+ bool "TAGADA"
diff --git a/src/mainboard/scaleway/tagada/Makefile.inc b/src/mainboard/scaleway/tagada/Makefile.inc
new file mode 100644
index 0000000..2c8186f
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/Makefile.inc
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 - 2017 Intel Corporation.
+## Copyright (C) 2017 Online SAS.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += hsio.c
+
+ramstage-y += ramstage.c
+ramstage-y += hsio.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
+
+CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/
diff --git a/src/mainboard/scaleway/tagada/acpi/mainboard.asl b/src/mainboard/scaleway/tagada/acpi/mainboard.asl
new file mode 100644
index 0000000..41da382
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/acpi/mainboard.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+Scope (\_SB)
+{
+ Device (PWRB)
+ {
+ Name(_HID, EisaId("PNP0C0C"))
+
+ // Wake
+ Name(_PRW, Package(){0x1d, 0x05})
+ }
+}
diff --git a/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl b/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl
new file mode 100644
index 0000000..e253cea
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl
@@ -0,0 +1,187 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* This is board specific information: IRQ routing */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // [GREG]: Global Registers
+ Package() { 0x0004ffff, 0, 0, 16 },
+
+ // [RCEC]: Root Complex Event Collector
+ Package() { 0x0005ffff, 0, 0, 23 },
+
+ // [VRP2]: Virtual root port 2
+ Package() { 0x0006ffff, 2, 0, 18 },
+
+ // [PEX0]: PCI Express Port 0
+ Package() { 0x0009ffff, 0, 0, 16 },
+
+ // [PEX1]: PCI Express Port 1
+ Package() { 0x000affff, 1, 0, 17 },
+
+ // [PEX2]: PCI Express Port 2
+ Package() { 0x000bffff, 2, 0, 18 },
+
+ // [PEX3]: PCI Express Port 3
+ Package() { 0x000cffff, 3, 0, 19 },
+
+ // [PEX4]: PCI Express Port 4
+ Package() { 0x000effff, 0, 0, 20 },
+
+ // [PEX5]: PCI Express Port 5
+ Package() { 0x000fffff, 1, 0, 21 },
+
+ // [PEX6]: PCI Express Port 6
+ Package() { 0x0010ffff, 2, 0, 22 },
+
+ // [PEX7]: PCI Express Port 7
+ Package() { 0x0011ffff, 3, 0, 23 },
+
+ // [SMB1]: SMBus controller
+ Package() { 0x0012ffff, 0, 0, 16 },
+
+ // [SAT0]: SATA controller 0
+ Package() { 0x0013ffff, 0, 0, 20 },
+
+ // [SAT1]: SATA controller 1
+ Package() { 0x0014ffff, 0, 0, 21 },
+
+ // [XHC0]: XHCI USB controller
+ Package() { 0x0015ffff, 0, 0, 19 },
+
+ // [VRP0]: Virtual root port 0
+ Package() { 0x0016ffff, 0, 0, 16 },
+
+ // [VRP1]: Virtual root port 1
+ Package() { 0x0017ffff, 1, 0, 17 },
+
+ // [HECI]: ME HECI
+ Package() { 0x0018ffff, 0, 0, 16 },
+
+ // [HEC2]: ME HECI2
+ Package() { 0x0018ffff, 1, 0, 17 },
+
+ // [MEKT]: MEKT on PCH
+ Package() { 0x0018ffff, 2, 0, 18 },
+
+ // [HEC3]: ME HECI3
+ Package() { 0x0018ffff, 3, 0, 19 },
+
+ // [UAR0]: UART 0
+ Package() { 0x001affff, 0, 0, 16 },
+
+ // [UAR1]: UART 1
+ Package() { 0x001affff, 1, 0, 17 },
+
+ // [UAR2]: UART 2
+ Package() { 0x001affff, 2, 0, 18 },
+
+ // [EMMC]: eMMC
+ Package() { 0x001cffff, 0, 0, 16 },
+
+ // [P2SB]: Primary to sideband bridge
+ // [SMB0]: SMBus controller
+ // [NPK0]: Northpeak DFX
+ Package() { 0x001fffff, 0, 0, 23 },
+ })
+ } Else {
+ Return (Package() {
+ // [GREG]: Global Registers 0:4.0
+ Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+ // [RCEC]: Root Complex Event Collector 0:5.0
+ Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+
+ // [VRP2]: Virtual root port 2 0:6.0
+ Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+ // [PEX0]: PCI Express Port 0 0:9.0
+ Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+ // [PEX1]: PCI Express Port 1 0:a.0
+ Package() { 0x000affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+
+ // [PEX2]: PCI Express Port 2 0:b.0
+ Package() { 0x000bffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+ // [PEX3]: PCI Express Port 3 0:c.0
+ Package() { 0x000cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+
+ // [PEX4]: PCI Express Port 4 0:e.0
+ Package() { 0x000effff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+
+ // [PEX5]: PCI Express Port 5 0:f.0
+ Package() { 0x000fffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
+
+ // [PEX6]: PCI Express Port 6 0:10.0
+ Package() { 0x0010ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 },
+
+ // [PEX7]: PCI Express Port 7 0:11.0
+ Package() { 0x0011ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 },
+
+ // [SMB1]: SMBus controller 0:12.0
+ Package() { 0x0012ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+ // [SAT0]: SATA controller 0 0:13.0
+ Package() { 0x0013ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+
+ // [SAT1]: SATA controller 1 0:14.0
+ Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+
+ // [XHC0]: XHCI USB controller 0:15.0
+ Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+
+ // [VRP0]: Virtual root port 0 0:16.0
+ Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+ // [VRP1]: Virtual root port 1 0:17.0
+ Package() { 0x0017ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+
+ // [HECI]: ME HECI 0:18.0
+ Package() { 0x0018ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+ // [HEC2]: ME HECI2 0:18.1
+ Package() { 0x0018ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+
+ // [MEKT]: MEKT on PCH 0:18.2
+ Package() { 0x0018ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+ // [HEC3]: ME HECI3 0:18.3
+ Package() { 0x0018ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+
+ // [UAR0]: UART 0 0:1a.0
+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+ // [UAR1]: UART 1 0:1a.1
+ Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+
+ // [UAR2]: UART 2 0:1a.2
+ Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+ // [EMMC]: eMMC 0:1c.0
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+ // [P2SB]: Primary to sideband bridge
+ // [SMB0]: SMBus controller
+ // [NPK0]: Northpeak DFX
+ Package() { 0x001ffffF, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+ })
+ }
+}
diff --git a/src/mainboard/scaleway/tagada/acpi/platform.asl b/src/mainboard/scaleway/tagada/acpi/platform.asl
new file mode 100644
index 0000000..ea66a9f
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/acpi/platform.asl
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 - 2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/scaleway/tagada/acpi/thermal.asl b/src/mainboard/scaleway/tagada/acpi/thermal.asl
new file mode 100644
index 0000000..5f9164d
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/acpi/thermal.asl
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+ // Thermal Zone
+
+Scope (\_TZ)
+{
+}
diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c
new file mode 100644
index 0000000..acbdb30
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/acpi_tables.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+
+extern const unsigned char AmlCode[];
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ acpi_init_gnvs(gnvs);
+
+ /* Disable USB ports in S5 */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* TPM Present */
+ gnvs->tpmp = 0;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2,
+ IO_APIC_ADDR, 0);
+
+ current = acpi_madt_irq_overrides(current);
+
+ return current;
+}
diff --git a/src/mainboard/scaleway/tagada/board_info.txt b/src/mainboard/scaleway/tagada/board_info.txt
new file mode 100644
index 0000000..2b94d46
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Scaleway
+Board name: Tagada
+Category: server
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/scaleway/tagada/devicetree.cb b/src/mainboard/scaleway/tagada/devicetree.cb
new file mode 100644
index 0000000..acf56a0
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/devicetree.cb
@@ -0,0 +1,75 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 - 2017 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip soc/intel/denverton_ns
+
+ # configure pirq routing
+ register "pirqa_routing" = "11"
+ register "pirqb_routing" = "10"
+ register "pirqc_routing" = "06"
+ register "pirqd_routing" = "07"
+ register "pirqe_routing" = "12"
+ register "pirqf_routing" = "14"
+ register "pirqg_routing" = "15"
+ register "pirqh_routing" = "15"
+ # configure device interrupt routing
+ register "ir00_routing" = "0x3217" # IR00, Dev31
+ register "ir01_routing" = "0x3210" # IR01, Dev22
+ register "ir02_routing" = "0x3211" # IR02, Dev23
+ register "ir03_routing" = "0x3217" # IR03, Dev5
+ register "ir04_routing" = "0x3212" # IR04, Dev6
+ register "ir05_routing" = "0x3210" # IR05, Dev24
+ register "ir06_routing" = "0x3214" # IR06, Dev19
+ register "ir07_routing" = "0x3210" # IR07, Dev9/10/11/12
+ register "ir08_routing" = "0x7654" # IR08, Dev14/15/16/17
+ register "ir09_routing" = "0x3213" # IR09, Dev21
+ register "ir10_routing" = "0x3210" # IR10, Dev26/18
+ register "ir11_routing" = "0x3215" # IR11, Dev20
+ register "ir12_routing" = "0x3210" # IR12, Dev27
+ # configure interrupt polarity control
+ register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
+ register "ipc1" = "0x00000000" # IPC1
+ register "ipc2" = "0x00000000" # IPC2
+ register "ipc3" = "0x00000000" # IPC3
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 04.0 on end # RAS
+ device pci 05.0 on end # RCEC(Root Complex Event Collector)
+ device pci 06.0 on end # Virtual root port 2 (QAT)
+ device pci 09.0 on end # PCI Express Port 0, cluster #0, x4
+ device pci 10.0 on end # PCI Express Port 6, cluster #1, x2
+ device pci 11.0 on end # PCI Express Port 7, cluster #1, x2
+ device pci 12.0 on end # SMBus Controller 1
+ device pci 13.0 on end # SATA Controller 0
+ device pci 14.0 on end # SATA Controller 1
+ device pci 15.0 on end # XHCI USB Controller
+ device pci 16.0 on end # Virtual root port 0 (10GBE0)
+ device pci 17.0 on end # Virtual root port 1 (10GBE1)
+ device pci 18.0 on end # CSME HECI 1
+ device pci 1a.0 on end # UART 0
+ device pci 1a.1 off end # UART 1
+ device pci 1a.2 off end # UART 2
+ device pci 1c.0 on end # eMMC
+ device pci 1f.0 on end # LPC bridge
+ device pci 1f.2 on end # PMC/ACPI
+ device pci 1f.4 on end # SMBus Controller 0
+ device pci 1f.5 on end # SPI Controller
+ end
+end
diff --git a/src/mainboard/scaleway/tagada/dsdt.asl b/src/mainboard/scaleway/tagada/dsdt.asl
new file mode 100644
index 0000000..4e66d17
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 - 2009 coresystems GmbH
+ * Copyright 2011 Google Inc.
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include "acpi/mainboard.asl"
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ // Thermal Handler
+ #include "acpi/thermal.asl"
+
+ // global NVS and variables
+ #include <soc/intel/denverton_ns/acpi/globalnvs.asl>
+
+ #include <soc/intel/denverton_ns/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/denverton_ns/acpi/northcluster.asl>
+ #include <soc/intel/denverton_ns/acpi/southcluster.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <soc/intel/denverton_ns/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/scaleway/tagada/fadt.c b/src/mainboard/scaleway/tagada/fadt.c
new file mode 100644
index 0000000..9f41f64
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/fadt.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 - 2009 coresystems GmbH
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <string.h>
+#include <arch/acpi.h>
+
+#include <soc/acpi.h>
+#include <soc/soc_util.h>
+
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+
+ memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+ memcpy_s(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy_s(header->oem_id, OEM_ID, 6);
+ memcpy_s(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy_s(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long)facs;
+ fadt->dsdt = (unsigned long)dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER;
+
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ acpi_fill_in_fadt(fadt);
+
+ header->checksum = acpi_checksum((void *)fadt, header->length);
+}
diff --git a/src/mainboard/scaleway/tagada/gpio.h b/src/mainboard/scaleway/tagada/gpio.h
new file mode 100644
index 0000000..d8468f6
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/gpio.h
@@ -0,0 +1,636 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ * Copyright (C) 2017 - 2018 Online SAS.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MAINBOARD_GPIO_H
+#define _MAINBOARD_GPIO_H
+
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+const struct pad_config tagada_gpio_config[] = {
+ // GBE0_SDP0 (GPIO_14) NC
+/*ME { NORTH_ALL_GBE0_SDP0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } }, */
+ // GBE1_SDP0 (GPIO_15) NC
+ { NORTH_ALL_GBE1_SDP0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE2_I2C_CLK (GPIO_16) NC
+ { NORTH_ALL_GBE0_SDP1, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE2_I2C_DATA (GPIO_17) NC
+ { NORTH_ALL_GBE1_SDP1, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE2_SDP0 (GPIO_18) NC
+ { NORTH_ALL_GBE0_SDP2, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE3_SDP0 (GPIO_19) NC
+ { NORTH_ALL_GBE1_SDP2, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE3_I2C_CLK (GPIO_20) NC
+ { NORTH_ALL_GBE0_SDP3, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE3_I2C_DATA (GPIO_21) NC
+ { NORTH_ALL_GBE1_SDP3, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE2_LED0 (GPIO_22) Z1:NC / A0:ETH0_LED0
+ { NORTH_ALL_GBE2_LED0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE2_LED1 (GPIO_23) Z1:NC / A0:ETH0_LED1
+ { NORTH_ALL_GBE2_LED1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE0_I2C_CLK (GPIO_24) NC
+ { NORTH_ALL_GBE0_I2C_CLK, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE0_I2C_DATA (GPIO_25) NC
+ { NORTH_ALL_GBE0_I2C_DATA, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE1_I2C_CLK (GPIO_26) NC
+ { NORTH_ALL_GBE1_I2C_CLK, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE1_I2C_DATA (GPIO_27) NC
+ { NORTH_ALL_GBE1_I2C_DATA, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_RXD0 (GPIO_28) NC
+ { NORTH_ALL_NCSI_RXD0, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_CLK_IN (GPIO_29) Pull Down
+ { NORTH_ALL_NCSI_CLK_IN, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_RXD1 (GPIO_30) NC
+ { NORTH_ALL_NCSI_RXD1, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_CRS_DV (GPIO_31) NC
+ { NORTH_ALL_NCSI_CRS_DV, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_ARB_IN (GPIO_32) NC
+ { NORTH_ALL_NCSI_ARB_IN, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_TX_EN (GPIO_33) Pull Down
+ { NORTH_ALL_NCSI_TX_EN, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_TXD0 (GPIO_34) Pull Down
+ { NORTH_ALL_NCSI_TXD0, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_TXD1 (GPIO_35) Pull Down
+ { NORTH_ALL_NCSI_TXD1, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // NCSI_ARB_OUT (GPIO_36) NC
+ { NORTH_ALL_NCSI_ARB_OUT, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE0_LED0 (GPIO_37) Z1:ETH0_LED0 / A1:ETH1_LED0
+ { NORTH_ALL_GBE0_LED0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE0_LED1 (GPIO_38) Z1:ETH0_LED1 / A1:ETH1_LED1
+ { NORTH_ALL_GBE0_LED1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE1_LED0 (GPIO_39) Z1:ETH1_LED0 / A1:NC
+ { NORTH_ALL_GBE1_LED0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE1_LED1 (GPIO_40) Z1:ETH1_LED1 / A1:NC
+ { NORTH_ALL_GBE1_LED1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // ADR-COMPLETE (GPIO_0) LFFF: DVT_GPIO<0> : BOOTED, output
+ { NORTH_ALL_GPIO_0, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock } },
+ // PCIE_CLKREQ0_N (GPIO_41) Pull Up
+ { NORTH_ALL_PCIE_CLKREQ0_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PCIE_CLKREQ1_N (GPIO_42) Pull Up
+ { NORTH_ALL_PCIE_CLKREQ1_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PCIE_CLKREQ2_N (GPIO_43) Pull Up
+ { NORTH_ALL_PCIE_CLKREQ2_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PCIE_CLKREQ3_N (GPIO_44) Pull Up
+ { NORTH_ALL_PCIE_CLKREQ3_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PCIE_CLKREQ4_N (GPIO_45) Pull Up
+ { NORTH_ALL_PCIE_CLKREQ4_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE_MDC (GPIO_1) NC
+ { NORTH_ALL_GPIO_1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE_MDIO (GPIO_2) NC
+ { NORTH_ALL_GPIO_2, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SVID_ALERT_N (GPIO_47) SVID_ALERTn
+ { NORTH_ALL_SVID_ALERT_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SVID_DATA (GPIO_48) SVID_DATA
+ { NORTH_ALL_SVID_DATA, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SVID_CLK (GPIO_49) SVID_CLK
+ { NORTH_ALL_SVID_CLK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // THERMTRIP_N (GPIO_50) SOC_THERMTRIPn Pull Up
+ { NORTH_ALL_THERMTRIP_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PROCHOT_N (GPIO_51) PROCHOTn Pull Up
+ { NORTH_ALL_PROCHOT_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // MEMHOT_N (GPIO_52) SOC_MEMHOTn
+ { NORTH_ALL_MEMHOT_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT_CLK0 (GPIO_53) NC
+ { SOUTH_DFX_DFX_PORT_CLK0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT_CLK1 (GPIO_54) NC
+ { SOUTH_DFX_DFX_PORT_CLK1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT0 (GPIO_55) NC
+ { SOUTH_DFX_DFX_PORT0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT1 (GPIO_56) NC
+ { SOUTH_DFX_DFX_PORT1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT2 (GPIO_57) NC
+ { SOUTH_DFX_DFX_PORT2, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT3 (GPIO_58) NC
+ { SOUTH_DFX_DFX_PORT3, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT4 (GPIO_59) NC
+ { SOUTH_DFX_DFX_PORT4, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT5 (GPIO_60) NC
+ { SOUTH_DFX_DFX_PORT5, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT6 (GPIO_61) NC
+ { SOUTH_DFX_DFX_PORT6, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT7 (GPIO_62) NC
+ { SOUTH_DFX_DFX_PORT7, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT8 (GPIO_63) NC
+ { SOUTH_DFX_DFX_PORT8, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT9 (GPIO_134) NC
+ { SOUTH_DFX_DFX_PORT9, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT10 (GPIO_135) NC
+ { SOUTH_DFX_DFX_PORT10, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT11 (GPIO_136) NC
+ { SOUTH_DFX_DFX_PORT11, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT12 (GPIO_137) NC
+ { SOUTH_DFX_DFX_PORT12, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT13 (GPIO_138) NC
+ { SOUTH_DFX_DFX_PORT13, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT14 (GPIO_139) NC
+ { SOUTH_DFX_DFX_PORT14, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // DFX_PORT15 (GPIO_140) NC
+ { SOUTH_DFX_DFX_PORT15, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SPI_TPM_CS_N (GPIO_12) HS_TCO_WDT NC (Possible Pull Up)
+ { SOUTH_GROUP0_GPIO_12, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB5_GBE_ALRT_N (GPIO_13) LAN_ALRTn Pull Up
+ { SOUTH_GROUP0_SMB5_GBE_ALRT_N, { GpioPadModeNative3, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PCIE_CLKREQ5_N (GPIO_98) Pull Up
+ { SOUTH_GROUP0_PCIE_CLKREQ5_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PCIE_CLKREQ6_N (GPIO_99) Pull Up
+ { SOUTH_GROUP0_PCIE_CLKREQ6_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PCIE_CLKREQ7_N (GPIO_100) Pull Up
+ { SOUTH_GROUP0_PCIE_CLKREQ7_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // UART0_RXD (GPIO_101) CONSOLE_RX
+ { SOUTH_GROUP0_UART0_RXD, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // UART0_TXD (GPIO_102) CONSOLE_TX
+ { SOUTH_GROUP0_UART0_TXD, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB5_GBE_CLK (GPIO_103) LAN_SLC Pull Up
+ { SOUTH_GROUP0_SMB5_GBE_CLK, { GpioPadModeNative3, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB_GBE_DATA (GPIO_104) LAN_SDA Pull UP
+ { SOUTH_GROUP0_SMB5_GBE_DATA, { GpioPadModeNative3, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // ERROR2_N (GPIO_105) ERRORn2
+ { SOUTH_GROUP0_ERROR2_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // ERROR1_N (GPIO_106) ERRORn1
+ { SOUTH_GROUP0_ERROR1_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // ERROR0_N (GPIO_107) ERRORn0 Pull Up
+ { SOUTH_GROUP0_ERROR0_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // IERR_N (CATERR_N) (GPIO_108) IERRn (HardStrap Pull Up)
+ { SOUTH_GROUP0_IERR_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // MCERR_N (GPIO_109) MCERR
+ { SOUTH_GROUP0_MCERR_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB0_LEG_CLK (GPIO_110) LEG_SCL Pull Up
+ { SOUTH_GROUP0_SMB0_LEG_CLK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB0_LEG_DATA (GPIO_111) LEG_SDA Pull Up
+ { SOUTH_GROUP0_SMB0_LEG_DATA, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB0_LEG_ALRT_N (GPIO_112) Pull Up
+ { SOUTH_GROUP0_SMB0_LEG_ALRT_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB1_HOST_DATA (GPIO_113) HOST_SDA Pull Up
+/*ME { SOUTH_GROUP0_SMB1_HOST_DATA, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },*/
+ // SMB1_HOST_CLK (GPIO_114) HOST_SCL Pull Up
+/*ME { SOUTH_GROUP0_SMB1_HOST_CLK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },*/
+ // SMB2_PECI_DATA (GPIO_115) Pull Up
+ { SOUTH_GROUP0_SMB2_PECI_DATA, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB2_PECI_CLK (GPIO_116) Pull Up
+ { SOUTH_GROUP0_SMB2_PECI_CLK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB4_CSME0_DATA (GPIO_117) ME_SDA Pull Up
+/*ME { SOUTH_GROUP0_SMB4_CSME0_DATA, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },*/
+ // SMB4_CSME0_CLK (GPIO_118) ME_SCL Pull Up
+/*ME { SOUTH_GROUP0_SMB4_CSME0_CLK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },*/
+ // SMB4_CSME0_ALRT_N (GPIO_119) ME_ALRTn Pull Up
+ { SOUTH_GROUP0_SMB4_CSME0_ALRT_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // USB_OC0_N (GPIO_120) Pull Up
+ { SOUTH_GROUP0_USB_OC0_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // FLEX_CLK_SE0 (GPIO_121) NC
+ { SOUTH_GROUP0_FLEX_CLK_SE0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // FLEX_CLK_SE1 (GPIO_122) NC
+ { SOUTH_GROUP0_FLEX_CLK_SE1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // GBE3_LED1 (GPIO_4) LFFF: M2A_CFGn : M2A_SATAn, input
+ { SOUTH_GROUP0_GPIO_4, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB3_IE0_CLK (GPIO_5) LFFF: M2B_CFGn : M2B_SATAn, input
+ { SOUTH_GROUP0_GPIO_5, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB3_IE0_DATA (GPIO_6) NC
+ { SOUTH_GROUP0_GPIO_6, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB3_IE0_ALERT_N (GPIO_7) NC
+ { SOUTH_GROUP0_GPIO_7, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SATA0_LED (GPIO_90) SATA_LED0 Pull Up
+ { SOUTH_GROUP0_SATA0_LED_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SATA1_LED (GPIO_91) SATA_LED1 Pull Up
+ { SOUTH_GROUP0_SATA1_LED_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SATA_PDETECT0 (GPIO_92) Pull Up
+ { SOUTH_GROUP0_SATA_PDETECT0, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SATA_PDETECT1 (GPIO_93) Pull Up
+ { SOUTH_GROUP0_SATA_PDETECT1, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // UART1_RTS (GPIO_94) NC (Possible Pull Up)
+ { SOUTH_GROUP0_SATA0_SDOUT, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // UART1_CTS (GPIO_95) NC (Possible Pull Up)
+ { SOUTH_GROUP0_SATA1_SDOUT, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // UART1_RXD (GPIO_96) NC
+ { SOUTH_GROUP0_UART1_RXD, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // UART1_TXD (GPIO_97) NC
+ { SOUTH_GROUP0_UART1_TXD, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB6_CSME1_DATA (GPIO_8) LFFF: DVT_GPIO<1> : Baud select, input
+ { SOUTH_GROUP0_GPIO_8, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB6_CSME1_CLK (GPIO_9) LFFF: DVT_GPIO<2> : Verbose Traces, input
+ { SOUTH_GROUP0_GPIO_9, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // TCK (GPIO_141) n/a NC
+ { SOUTH_GROUP0_TCK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // TRST_N (GPIO_142) n/a NC
+ { SOUTH_GROUP0_TRST_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // TMS (GPIO_143) n/a NC
+ { SOUTH_GROUP0_TMS, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // TDI (GPIO_144) n/a NC
+ { SOUTH_GROUP0_TDI, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // TDO (GPIO_145) n/a NC
+ { SOUTH_GROUP0_TDO, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // CX_PRDY_N (GPIO_146) NC
+ { SOUTH_GROUP0_CX_PRDY_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // CX-PREQ_N (GPIO_147) Pull Up
+ { SOUTH_GROUP0_CX_PREQ_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // ME_RECVR_HDR (GPIO_148) ME_RECVR Pull Up
+/*ME { SOUTH_GROUP0_CTBTRIGINOUT, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },*/
+ // ADV_DBG_DFX_HDR (GPIO_149) NC
+ { SOUTH_GROUP0_CTBTRIGOUT, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LAD2_SPI_IRQ_N (GPIO_150) NC
+ { SOUTH_GROUP0_DFX_SPARE2, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB_PECI_ALRT_N (GPIO_151) Pull Up
+ { SOUTH_GROUP0_DFX_SPARE3, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SMB_CSME1_ALRT_N (GPIO_152) NC
+ { SOUTH_GROUP0_DFX_SPARE4, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SUSPWRDNACK (GPIO_79) SUSPWRDNACK Pull Up
+ { SOUTH_GROUP1_SUSPWRDNACK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PMU_SUSCLK (GPIO_80) PMU_SUSCLK
+ { SOUTH_GROUP1_PMU_SUSCLK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // ADR_TRIGGER_N (GPIO_81) Pull Down
+ { SOUTH_GROUP1_ADR_TRIGGER, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PMU_SLP_S45_N (GPIO_82) SLP_S45n
+ { SOUTH_GROUP1_PMU_SLP_S45_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PMU_SLP_S3_N (GPIO_83) SLP_S3n
+ { SOUTH_GROUP1_PMU_SLP_S3_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PMU_WAKE_N (GPIO_84) PMU_WAKEn Pull Up
+ { SOUTH_GROUP1_PMU_WAKE_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PMU_PWRBTN_N (GPIO_85) PWNBTNn
+ { SOUTH_GROUP1_PMU_PWRBTN_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PMU_RESETBUTTON_N (GPIO_86) RSTBTNn
+ { SOUTH_GROUP1_PMU_RESETBUTTON_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PMU_PLTRST_N (GPIO_87) PLTRSTn
+ { SOUTH_GROUP1_PMU_PLTRST_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // PMU_SUS_STAT_N (GPIO_88) SUS_STATn
+ { SOUTH_GROUP1_SUS_STAT_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // TDB_CIO_PLUG_EVENT (GPIO_89) NC
+ { SOUTH_GROUP1_SLP_S0IX_N, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SPI_CS0_N (GPIO_72) SPI_CS0
+ { SOUTH_GROUP1_SPI_CS0_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SPI_CS1_N (GPIO_73) NC
+ { SOUTH_GROUP1_SPI_CS1_N, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SPI_MOSI_IO0 (GPIO_74) SPI_MOSI
+ { SOUTH_GROUP1_SPI_MOSI_IO0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SPI_MISO_IO1 (GPIO_75) SPI_MISO
+ { SOUTH_GROUP1_SPI_MISO_IO1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SPI_IO2 (GPIO_76) NC
+ { SOUTH_GROUP1_SPI_IO2, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SPI_IO3 (GPIO_77) NC
+ { SOUTH_GROUP1_SPI_IO3, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // SPI_CLK (GPIO_78) SPI_CLK
+ { SOUTH_GROUP1_SPI_CLK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_AD0 (GPIO_64) NC
+ { SOUTH_GROUP1_ESPI_IO0, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_AD1 (GPIO_65) NC
+ { SOUTH_GROUP1_ESPI_IO1, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_AD2 (GPIO_66) NC
+ { SOUTH_GROUP1_ESPI_IO2, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_AD3 (GPIO_67) NC
+ { SOUTH_GROUP1_ESPI_IO3, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_FRAME_N (GPIO_68) NC
+ { SOUTH_GROUP1_ESPI_CS0_N, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_CLKOUT0 (GPIO_69) NC
+ { SOUTH_GROUP1_ESPI_CLK, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_CLKOUT1 (GPIO_70) NC
+ { SOUTH_GROUP1_ESPI_RST_N, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_CLKRUN_N (GPIO_71) Pull Up
+ { SOUTH_GROUP1_ESPI_ALRT0_N, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // MFG_MODE_HDR (GPIO_10) MFG_MODE Pull Up
+ { SOUTH_GROUP1_GPIO_10, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // LPC_SERIRQ (GPIO_11) NC
+ { SOUTH_GROUP1_GPIO_11, { GpioPadModeNative2, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-CMD (GPIO_123) NC
+ { SOUTH_GROUP1_EMMC_CMD, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-CSTROBE (GPIO_124) NC
+ { SOUTH_GROUP1_EMMC_STROBE, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-CLK (GPIO_125) NC
+ { SOUTH_GROUP1_EMMC_CLK, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-D0 (GPIO_126) NC
+ { SOUTH_GROUP1_EMMC_D0, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-D1 (GPIO_127) NC
+ { SOUTH_GROUP1_EMMC_D1, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-D2 (GPIO_128) NC
+ { SOUTH_GROUP1_EMMC_D2, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-D3 (GPIO_129) NC
+ { SOUTH_GROUP1_EMMC_D3, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-D4 (GPIO_130) NC
+ { SOUTH_GROUP1_EMMC_D4, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-D5 (GPIO_131) NC
+ { SOUTH_GROUP1_EMMC_D5, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-D6 (GPIO_132) NC
+ { SOUTH_GROUP1_EMMC_D6, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },
+ // EMMC-D7 (GPIO_133) NC
+ { SOUTH_GROUP1_EMMC_D7, { GpioPadModeNative1, GpioHostOwnGpio,
+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },
+ // IE_ROM GPIO (GPIO_3) HS_TSO NC (Possible Pull Up)
+ { SOUTH_GROUP1_GPIO_3, { GpioPadModeGpio, GpioHostOwnGpio,
+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,
+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },
+};
+#endif
+
+#endif /* _MAINBOARD_GPIO_H */
diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c
new file mode 100644
index 0000000..a8a2035
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/hsio.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017 - 2018 Online SAS.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <hsio.h>
+#include <soc/fiamux.h>
+
+size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config)
+{
+ size_t num;
+ num = ARRAY_SIZE(tagada_hsio_config);
+ (*p_hsio_config) = (BL_HSIO_INFORMATION *)tagada_hsio_config;
+ return num;
+}
diff --git a/src/mainboard/scaleway/tagada/hsio.h b/src/mainboard/scaleway/tagada/hsio.h
new file mode 100644
index 0000000..e49fefd
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/hsio.h
@@ -0,0 +1,631 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016-2017 Intel Corporation.
+ * Copyright (C) 2017 - 2018 Online SAS.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MAINBOARD_HSIO_H
+#define _MAINBOARD_HSIO_H
+
+#include <fsp/util.h>
+
+#ifndef __ACPI__
+const BL_HSIO_INFORMATION tagada_hsio_config[] = {
+ /*
+ * Supported Lanes:
+ * 20
+ *
+ * Bifurcation:
+ * PCIE cluster #0: x4x4
+ * PCIE cluster #1: x2x2x2x2 (used for M2)
+ *
+ * FIA MUX config:
+ * Lane[00:03]-> disconnected
+ * Lane[08:11]-> 4 SATA side connectors
+ * Lane[12:15]-> 4 PCIe or 2 SATA (12,14) on M2 Connectors.
+ * M2 modules are detected; configuration updated by coreboot
+ * Lane[19]->USB3 rear I/O panel connector
+ */
+
+ /* SKU HSIO 20 (pcie [12-15] sata [8-11,12,14] usb [19]) */
+ {BL_SKU_HSIO_20,
+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
+ {/* ME_FIA_MUX_CONFIG */
+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
+
+ /* ME_FIA_SATA_CONFIG */
+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE04) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE05) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE06) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE07) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE08) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE09) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE10) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE11) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE12) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE13) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE14) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE15) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE16) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE17) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE18) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE19)},
+
+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_7) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_7)} } },
+
+ /* SKU HSIO 12 (pcie [12-15] sata [8-11,12,14] usb [19]) */
+ {BL_SKU_HSIO_12,
+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
+ {/* ME_FIA_MUX_CONFIG */
+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
+
+ /* ME_FIA_SATA_CONFIG */
+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE04) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE05) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE06) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE07) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE08) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE09) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE10) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE11) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE12) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE13) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE14) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE15) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE16) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE17) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE18) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE19)},
+
+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG( BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_7) |
+
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_7)} } },
+
+ /* SKU HSIO 10 (pcie [12-15] sata [8-11,12,14] usb [19]) */
+ {BL_SKU_HSIO_10,
+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
+ {/* ME_FIA_MUX_CONFIG */
+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
+
+ /* ME_FIA_SATA_CONFIG */
+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE04) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE05) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE06) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE07) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE08) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE09) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE10) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE11) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE12) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE13) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE14) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE15) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE16) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE17) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE18) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE19)},
+
+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_7) |
+
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_7)} } },
+
+ /* SKU HSIO 8 (pcie [12-14] sata [8-11,12,14] usb [19]) */
+ {BL_SKU_HSIO_08,
+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
+ {/* ME_FIA_MUX_CONFIG */
+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},
+
+ /* ME_FIA_SATA_CONFIG */
+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE04) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE05) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE06) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE07) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE08) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE09) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE10) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE11) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE12) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE13) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE14) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE15) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE16) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE17) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE18) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE19)},
+
+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_7) |
+
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_7)} } },
+
+ /* SKU HSIO 6 (pcie [12,14] sata [8-11,12,14] usb []) */
+ {BL_SKU_HSIO_06,
+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},
+ {/* ME_FIA_MUX_CONFIG */
+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |
+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE19)},
+
+ /* ME_FIA_SATA_CONFIG */
+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE04) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE05) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE06) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE07) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE08) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE09) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE10) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,
+ BL_FIA_SATA_LANE11) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE12) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE13) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE14) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE15) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE16) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE17) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE18) |
+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,
+ BL_FIA_SATA_LANE19)},
+
+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */
+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,
+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,
+ BL_FIA_PCIE_ROOT_PORT_7) |
+
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_0) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_1) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_2) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_3) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_4) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_5) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_6) |
+ BL_FIA_PCIE_ROOT_PORT_CONFIG(
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,
+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,
+ BL_FIA_PCIE_ROOT_PORT_7)} } }
+};
+#endif
+#endif /* _MAINBOARD_HSIO_H */
diff --git a/src/mainboard/scaleway/tagada/ramstage.c b/src/mainboard/scaleway/tagada/ramstage.c
new file mode 100644
index 0000000..0aa6f13
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/ramstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 - 2017 Intel Corporation
+ * Copyright (C) 2017 - 2018 Online SAS.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <console/console.h>
+#include <fsp/api.h>
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+ /* Disable eMMC */
+ params->FspsConfig.PcdEnableEmmc = 0;
+}
diff --git a/src/mainboard/scaleway/tagada/romstage.c b/src/mainboard/scaleway/tagada/romstage.c
new file mode 100644
index 0000000..d6a1282
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/romstage.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corp.
+ * Copyright (C) 2017 - 2018 Online SAS.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "gpio.h"
+#include <console/console.h>
+#include <fsp/api.h>
+#include <fsp/soc_binding.h>
+#include <string.h>
+
+void mainboard_config_gpios(void);
+void mainboard_memory_init_params(FSPM_UPD *mupd);
+
+/*
+* Configure GPIO depend on platform
+*/
+void mainboard_config_gpios(void)
+{
+ size_t num;
+ const struct pad_config *table;
+
+ /* Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization.
+ */
+ table = tagada_gpio_config;
+ num = ARRAY_SIZE(tagada_gpio_config);
+
+ if ((!table) || (!num)) {
+ printk(BIOS_ERR, "ERROR: No valid GPIO table found!\n");
+ return;
+ }
+
+ printk(BIOS_INFO, "GPIO table: 0x%x, entry num: 0x%x!\n",
+ (uint32_t)table, (uint32_t)num);
+ gpio_configure_pads(table, num);
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ mupd->FspmConfig.PcdFspDebugPrintErrorLevel = 3; // Verbose
+
+ // Enable Rmt and Fast Boot by default, RMT will be run only on first
+ // boot or when dimms change
+ mupd->FspmConfig.PcdMrcRmtSupport = 1;
+ mupd->FspmConfig.PcdFastBoot = 1;
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id4ecb760b9ab07ab168b252542dcaaea4636d655
Gerrit-Change-Number: 23782
Gerrit-PatchSet: 1
Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert at online.net>
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