<p>Julien Viard de Galbert has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23782">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/scaleway/tagada: Add Scalway Tagada Board<br><br>Change-Id: Id4ecb760b9ab07ab168b252542dcaaea4636d655<br>Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net><br>---<br>A src/mainboard/scaleway/Kconfig<br>A src/mainboard/scaleway/Kconfig.name<br>A src/mainboard/scaleway/tagada/Kconfig<br>A src/mainboard/scaleway/tagada/Kconfig.name<br>A src/mainboard/scaleway/tagada/Makefile.inc<br>A src/mainboard/scaleway/tagada/acpi/mainboard.asl<br>A src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl<br>A src/mainboard/scaleway/tagada/acpi/platform.asl<br>A src/mainboard/scaleway/tagada/acpi/thermal.asl<br>A src/mainboard/scaleway/tagada/acpi_tables.c<br>A src/mainboard/scaleway/tagada/board_info.txt<br>A src/mainboard/scaleway/tagada/devicetree.cb<br>A src/mainboard/scaleway/tagada/dsdt.asl<br>A src/mainboard/scaleway/tagada/fadt.c<br>A src/mainboard/scaleway/tagada/gpio.h<br>A src/mainboard/scaleway/tagada/hsio.c<br>A src/mainboard/scaleway/tagada/hsio.h<br>A src/mainboard/scaleway/tagada/ramstage.c<br>A src/mainboard/scaleway/tagada/romstage.c<br>19 files changed, 2,008 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/23782/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/scaleway/Kconfig b/src/mainboard/scaleway/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..2af3e29</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/Kconfig</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+if VENDOR_SCALEWAY</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+choice</span><br><span style="color: hsl(120, 100%, 40%);">+ prompt "Mainboard model"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+source "src/mainboard/scaleway/*/Kconfig.name"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endchoice</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+source "src/mainboard/scaleway/*/Kconfig"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_VENDOR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Scaleway"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # VENDOR_SCALEWAY</span><br><span>diff --git a/src/mainboard/scaleway/Kconfig.name b/src/mainboard/scaleway/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..abbc9e7</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config VENDOR_SCALEWAY</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Scaleway"</span><br><span>diff --git a/src/mainboard/scaleway/tagada/Kconfig b/src/mainboard/scaleway/tagada/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..53c1f6d</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/Kconfig</span><br><span>@@ -0,0 +1,36 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2014 - 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_SCALEWAY_TAGADA</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_DENVERTON_NS</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_16384</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default scaleway/tagada</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "TAGADA"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_VENDOR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Scaleway"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # BOARD_SCALEWAY_TAGADA</span><br><span>diff --git a/src/mainboard/scaleway/tagada/Kconfig.name b/src/mainboard/scaleway/tagada/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..67e5e0a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SCALEWAY_TAGADA</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "TAGADA"</span><br><span>diff --git a/src/mainboard/scaleway/tagada/Makefile.inc b/src/mainboard/scaleway/tagada/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..2c8186f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/Makefile.inc</span><br><span>@@ -0,0 +1,24 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2014 - 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2017 Online SAS.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += hsio.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += ramstage.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += hsio.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/</span><br><span>diff --git a/src/mainboard/scaleway/tagada/acpi/mainboard.asl b/src/mainboard/scaleway/tagada/acpi/mainboard.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..41da382</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/acpi/mainboard.asl</span><br><span>@@ -0,0 +1,27 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 - 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Scope (\_SB)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PWRB)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_HID, EisaId("PNP0C0C"))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Wake</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_PRW, Package(){0x1d, 0x05})</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl b/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..e253cea</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl</span><br><span>@@ -0,0 +1,187 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 - 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* This is board specific information: IRQ routing */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// PCI Interrupt Routing</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Package() {</span><br><span style="color: hsl(120, 100%, 40%);">+ // [GREG]: Global Registers</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0004ffff, 0, 0, 16 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [RCEC]: Root Complex Event Collector</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0005ffff, 0, 0, 23 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [VRP2]: Virtual root port 2</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0006ffff, 2, 0, 18 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [PEX0]: PCI Express Port 0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0009ffff, 0, 0, 16 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [PEX1]: PCI Express Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x000affff, 1, 0, 17 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [PEX2]: PCI Express Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x000bffff, 2, 0, 18 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [PEX3]: PCI Express Port 3</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x000cffff, 3, 0, 19 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [PEX4]: PCI Express Port 4</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x000effff, 0, 0, 20 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [PEX5]: PCI Express Port 5</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x000fffff, 1, 0, 21 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [PEX6]: PCI Express Port 6</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0010ffff, 2, 0, 22 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [PEX7]: PCI Express Port 7</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0011ffff, 3, 0, 23 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [SMB1]: SMBus controller</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0012ffff, 0, 0, 16 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [SAT0]: SATA controller 0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0013ffff, 0, 0, 20 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [SAT1]: SATA controller 1</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0014ffff, 0, 0, 21 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [XHC0]: XHCI USB controller</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0015ffff, 0, 0, 19 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [VRP0]: Virtual root port 0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0016ffff, 0, 0, 16 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [VRP1]: Virtual root port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0017ffff, 1, 0, 17 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [HECI]: ME HECI</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0018ffff, 0, 0, 16 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [HEC2]: ME HECI2</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0018ffff, 1, 0, 17 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [MEKT]: MEKT on PCH</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0018ffff, 2, 0, 18 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [HEC3]: ME HECI3</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0018ffff, 3, 0, 19 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [UAR0]: UART 0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001affff, 0, 0, 16 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [UAR1]: UART 1</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001affff, 1, 0, 17 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [UAR2]: UART 2</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001affff, 2, 0, 18 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [EMMC]: eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001cffff, 0, 0, 16 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [P2SB]: Primary to sideband bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ // [SMB0]: SMBus controller</span><br><span style="color: hsl(120, 100%, 40%);">+ // [NPK0]: Northpeak DFX</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001fffff, 0, 0, 23 },</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Package() {</span><br><span style="color: hsl(120, 100%, 40%);">+ // [GREG]: Global Registers 0:4.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [RCEC]: Root Complex Event Collector 0:5.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [VRP2]: Virtual root port 2 0:6.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [PEX0]: PCI Express Port 0 0:9.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [PEX1]: PCI Express Port 1 0:a.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x000affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [PEX2]: PCI Express Port 2 0:b.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x000bffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [PEX3]: PCI Express Port 3 0:c.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x000cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [PEX4]: PCI Express Port 4 0:e.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x000effff, 0, \_SB.PCI0.LPCB.LNKE, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [PEX5]: PCI Express Port 5 0:f.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x000fffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [PEX6]: PCI Express Port 6 0:10.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0010ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [PEX7]: PCI Express Port 7 0:11.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0011ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [SMB1]: SMBus controller 0:12.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0012ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [SAT0]: SATA controller 0 0:13.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0013ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [SAT1]: SATA controller 1 0:14.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [XHC0]: XHCI USB controller 0:15.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [VRP0]: Virtual root port 0 0:16.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [VRP1]: Virtual root port 1 0:17.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0017ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [HECI]: ME HECI 0:18.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0018ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [HEC2]: ME HECI2 0:18.1</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0018ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [MEKT]: MEKT on PCH 0:18.2</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0018ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [HEC3]: ME HECI3 0:18.3</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0018ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [UAR0]: UART 0 0:1a.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [UAR1]: UART 1 0:1a.1</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [UAR2]: UART 2 0:1a.2</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [EMMC]: eMMC 0:1c.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // [P2SB]: Primary to sideband bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ // [SMB0]: SMBus controller</span><br><span style="color: hsl(120, 100%, 40%);">+ // [NPK0]: Northpeak DFX</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x001ffffF, 0, \_SB.PCI0.LPCB.LNKH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/scaleway/tagada/acpi/platform.asl b/src/mainboard/scaleway/tagada/acpi/platform.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..ea66a9f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/acpi/platform.asl</span><br><span>@@ -0,0 +1,70 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007 - 2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* The APM port can be used for generating software SMIs */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+OperationRegion (APMP, SystemIO, 0xb2, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+Field (APMP, ByteAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ APMC, 8, // APM command</span><br><span style="color: hsl(120, 100%, 40%);">+ APMS, 8 // APM status</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Port 80 POST */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+OperationRegion (POST, SystemIO, 0x80, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+Field (POST, ByteAcc, Lock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ DBG0, 8</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMI I/O Trap */</span><br><span style="color: hsl(120, 100%, 40%);">+Method(TRAP, 1, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Arg0, SMIF) // SMI Function</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0, TRP0) // Generate trap</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (SMIF) // Return value of SMI handler</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* The _PIC method is called by the OS to choose between interrupt</span><br><span style="color: hsl(120, 100%, 40%);">+ * routing via the i8259 interrupt controller or the APIC.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * _PIC is called with a parameter of 0 for i8259 configuration and</span><br><span style="color: hsl(120, 100%, 40%);">+ * with a parameter of 1 for Local Apic/IOAPIC configuration.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_PIC, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ // Remember the OS' IRQ routing choice.</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(Arg0, PICM)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* The _PTS method (Prepare To Sleep) is called before the OS is</span><br><span style="color: hsl(120, 100%, 40%);">+ * entering a sleep state. The sleep state number is passed in Arg0</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_PTS,1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* The _WAK method is called on system wakeup */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_WAK,1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Return(Package(){0,0})</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/scaleway/tagada/acpi/thermal.asl b/src/mainboard/scaleway/tagada/acpi/thermal.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..5f9164d</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/acpi/thermal.asl</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 - 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Thermal Zone</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Scope (\_TZ)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..acbdb30</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/acpi_tables.c</span><br><span>@@ -0,0 +1,61 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 - 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/ioapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpigen.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/smp/mpspec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+extern const unsigned char AmlCode[];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_gnvs(global_nvs_t *gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_init_gnvs(gnvs);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable USB ports in S5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s5u0 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s5u1 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TPM Present */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->tpmp = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long acpi_fill_madt(unsigned long current)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Local APICs */</span><br><span style="color: hsl(120, 100%, 40%);">+ current = acpi_create_madt_lapics(current);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IOAPIC */</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ IO_APIC_ADDR, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ current = acpi_madt_irq_overrides(current);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return current;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/scaleway/tagada/board_info.txt b/src/mainboard/scaleway/tagada/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..2b94d46</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/board_info.txt</span><br><span>@@ -0,0 +1,6 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Vendor name: Scaleway</span><br><span style="color: hsl(120, 100%, 40%);">+Board name: Tagada</span><br><span style="color: hsl(120, 100%, 40%);">+Category: server</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: n</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: y</span><br><span>diff --git a/src/mainboard/scaleway/tagada/devicetree.cb b/src/mainboard/scaleway/tagada/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..acf56a0</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/devicetree.cb</span><br><span>@@ -0,0 +1,75 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2014 - 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/denverton_ns</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # configure pirq routing</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqa_routing" = "11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqb_routing" = "10"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqc_routing" = "06"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqd_routing" = "07"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqe_routing" = "12"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqf_routing" = "14"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqg_routing" = "15"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqh_routing" = "15"</span><br><span style="color: hsl(120, 100%, 40%);">+ # configure device interrupt routing</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ir00_routing" = "0x3217" # IR00, Dev31</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ir01_routing" = "0x3210" # IR01, Dev22</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ir02_routing" = "0x3211" # IR02, Dev23</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ir03_routing" = "0x3217" # IR03, Dev5</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ir04_routing" = "0x3212" # IR04, Dev6</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ir05_routing" = "0x3210" # IR05, Dev24</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ir06_routing" = "0x3214" # IR06, Dev19</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ir07_routing" = "0x3210" # IR07, Dev9/10/11/12</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ir08_routing" = "0x7654" # IR08, Dev14/15/16/17</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ir09_routing" = "0x3213" # IR09, Dev21</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ir10_routing" = "0x3210" # IR10, Dev26/18</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ir11_routing" = "0x3215" # IR11, Dev20</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ir12_routing" = "0x3210" # IR12, Dev27</span><br><span style="color: hsl(120, 100%, 40%);">+ # configure interrupt polarity control</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ipc1" = "0x00000000" # IPC1</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ipc2" = "0x00000000" # IPC2</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ipc3" = "0x00000000" # IPC3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 04.0 on end # RAS</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 05.0 on end # RCEC(Root Complex Event Collector)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 06.0 on end # Virtual root port 2 (QAT)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 09.0 on end # PCI Express Port 0, cluster #0, x4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 10.0 on end # PCI Express Port 6, cluster #1, x2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 11.0 on end # PCI Express Port 7, cluster #1, x2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 on end # SMBus Controller 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.0 on end # SATA Controller 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # SATA Controller 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # XHCI USB Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # Virtual root port 0 (10GBE0)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 on end # Virtual root port 1 (10GBE1)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.0 on end # CSME HECI 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on end # UART 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.1 off end # UART 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.2 off end # UART 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on end # LPC bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # PMC/ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 on end # SMBus Controller 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 on end # SPI Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/scaleway/tagada/dsdt.asl b/src/mainboard/scaleway/tagada/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..4e66d17</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/dsdt.asl</span><br><span>@@ -0,0 +1,53 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007 - 2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2011 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 - 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock(</span><br><span style="color: hsl(120, 100%, 40%);">+ "dsdt.aml",</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02, // DSDT revision: ACPI v2.0</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREv4", // OEM id</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREBOOT", // OEM table id</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20110725 // OEM revision</span><br><span style="color: hsl(120, 100%, 40%);">+)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ // Some generic macros</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/platform.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/mainboard.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // General Purpose Events</span><br><span style="color: hsl(120, 100%, 40%);">+ //#include "acpi/gpe.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Thermal Handler</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/thermal.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // global NVS and variables</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/denverton_ns/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/denverton_ns/acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/denverton_ns/acpi/northcluster.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/denverton_ns/acpi/southcluster.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Chipset specific sleep states */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/denverton_ns/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/scaleway/tagada/fadt.c b/src/mainboard/scaleway/tagada/fadt.c</span><br><span>new file mode 100644</span><br><span>index 0000000..9f41f64</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/fadt.c</span><br><span>@@ -0,0 +1,50 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007 - 2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 - 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/soc_util.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_header_t *header = &(fadt->header);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ memset((void *)fadt, 0, sizeof(acpi_fadt_t));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy_s(header->signature, "FACP", 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ header->length = sizeof(acpi_fadt_t);</span><br><span style="color: hsl(120, 100%, 40%);">+ header->revision = 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy_s(header->oem_id, OEM_ID, 6);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy_s(header->oem_table_id, ACPI_TABLE_CREATOR, 8);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy_s(header->asl_compiler_id, ASLC, 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ header->asl_compiler_revision = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->firmware_ctrl = (unsigned long)facs;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->dsdt = (unsigned long)dsdt;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->model = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_firmware_ctl_l = (unsigned long)facs;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_firmware_ctl_h = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_dsdt_l = (unsigned long)dsdt;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->x_dsdt_h = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_fill_in_fadt(fadt);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ header->checksum = acpi_checksum((void *)fadt, header->length);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/scaleway/tagada/gpio.h b/src/mainboard/scaleway/tagada/gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..d8468f6</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/gpio.h</span><br><span>@@ -0,0 +1,636 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 - 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 - 2018 Online SAS.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _MAINBOARD_GPIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define _MAINBOARD_GPIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __ACPI__</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config tagada_gpio_config[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE0_SDP0 (GPIO_14) NC</span><br><span style="color: hsl(120, 100%, 40%);">+/*ME { NORTH_ALL_GBE0_SDP0, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } }, */</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE1_SDP0 (GPIO_15) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GBE1_SDP0, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE2_I2C_CLK (GPIO_16) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GBE0_SDP1, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE2_I2C_DATA (GPIO_17) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GBE1_SDP1, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE2_SDP0 (GPIO_18) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GBE0_SDP2, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE3_SDP0 (GPIO_19) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GBE1_SDP2, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE3_I2C_CLK (GPIO_20) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GBE0_SDP3, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE3_I2C_DATA (GPIO_21) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GBE1_SDP3, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE2_LED0 (GPIO_22) Z1:NC / A0:ETH0_LED0</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GBE2_LED0, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE2_LED1 (GPIO_23) Z1:NC / A0:ETH0_LED1</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GBE2_LED1, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE0_I2C_CLK (GPIO_24) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GBE0_I2C_CLK, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE0_I2C_DATA (GPIO_25) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GBE0_I2C_DATA, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE1_I2C_CLK (GPIO_26) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GBE1_I2C_CLK, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE1_I2C_DATA (GPIO_27) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GBE1_I2C_DATA, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // NCSI_RXD0 (GPIO_28) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_NCSI_RXD0, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // NCSI_CLK_IN (GPIO_29) Pull Down</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_NCSI_CLK_IN, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // NCSI_RXD1 (GPIO_30) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_NCSI_RXD1, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // NCSI_CRS_DV (GPIO_31) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_NCSI_CRS_DV, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // NCSI_ARB_IN (GPIO_32) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_NCSI_ARB_IN, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // NCSI_TX_EN (GPIO_33) Pull Down</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_NCSI_TX_EN, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // NCSI_TXD0 (GPIO_34) Pull Down</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_NCSI_TXD0, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // NCSI_TXD1 (GPIO_35) Pull Down</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_NCSI_TXD1, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // NCSI_ARB_OUT (GPIO_36) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_NCSI_ARB_OUT, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE0_LED0 (GPIO_37) Z1:ETH0_LED0 / A1:ETH1_LED0</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GBE0_LED0, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE0_LED1 (GPIO_38) Z1:ETH0_LED1 / A1:ETH1_LED1</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GBE0_LED1, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE1_LED0 (GPIO_39) Z1:ETH1_LED0 / A1:NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GBE1_LED0, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE1_LED1 (GPIO_40) Z1:ETH1_LED1 / A1:NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GBE1_LED1, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // ADR-COMPLETE (GPIO_0) LFFF: DVT_GPIO<0> : BOOTED, output</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GPIO_0, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // PCIE_CLKREQ0_N (GPIO_41) Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_PCIE_CLKREQ0_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // PCIE_CLKREQ1_N (GPIO_42) Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_PCIE_CLKREQ1_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // PCIE_CLKREQ2_N (GPIO_43) Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_PCIE_CLKREQ2_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // PCIE_CLKREQ3_N (GPIO_44) Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_PCIE_CLKREQ3_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // PCIE_CLKREQ4_N (GPIO_45) Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_PCIE_CLKREQ4_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE_MDC (GPIO_1) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GPIO_1, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE_MDIO (GPIO_2) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_GPIO_2, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SVID_ALERT_N (GPIO_47) SVID_ALERTn</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_SVID_ALERT_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SVID_DATA (GPIO_48) SVID_DATA</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_SVID_DATA, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SVID_CLK (GPIO_49) SVID_CLK</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_SVID_CLK, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // THERMTRIP_N (GPIO_50) SOC_THERMTRIPn Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_THERMTRIP_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // PROCHOT_N (GPIO_51) PROCHOTn Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_PROCHOT_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // MEMHOT_N (GPIO_52) SOC_MEMHOTn</span><br><span style="color: hsl(120, 100%, 40%);">+ { NORTH_ALL_MEMHOT_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT_CLK0 (GPIO_53) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT_CLK0, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT_CLK1 (GPIO_54) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT_CLK1, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT0 (GPIO_55) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT0, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT1 (GPIO_56) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT1, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT2 (GPIO_57) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT2, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT3 (GPIO_58) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT3, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT4 (GPIO_59) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT4, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT5 (GPIO_60) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT5, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT6 (GPIO_61) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT6, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT7 (GPIO_62) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT7, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT8 (GPIO_63) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT8, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT9 (GPIO_134) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT9, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT10 (GPIO_135) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT10, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT11 (GPIO_136) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT11, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT12 (GPIO_137) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT12, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT13 (GPIO_138) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT13, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT14 (GPIO_139) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT14, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // DFX_PORT15 (GPIO_140) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_DFX_DFX_PORT15, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SPI_TPM_CS_N (GPIO_12) HS_TCO_WDT NC (Possible Pull Up)</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_GPIO_12, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB5_GBE_ALRT_N (GPIO_13) LAN_ALRTn Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_SMB5_GBE_ALRT_N, { GpioPadModeNative3, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // PCIE_CLKREQ5_N (GPIO_98) Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_PCIE_CLKREQ5_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // PCIE_CLKREQ6_N (GPIO_99) Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_PCIE_CLKREQ6_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // PCIE_CLKREQ7_N (GPIO_100) Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_PCIE_CLKREQ7_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // UART0_RXD (GPIO_101) CONSOLE_RX</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_UART0_RXD, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // UART0_TXD (GPIO_102) CONSOLE_TX</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_UART0_TXD, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB5_GBE_CLK (GPIO_103) LAN_SLC Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_SMB5_GBE_CLK, { GpioPadModeNative3, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB_GBE_DATA (GPIO_104) LAN_SDA Pull UP</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_SMB5_GBE_DATA, { GpioPadModeNative3, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // ERROR2_N (GPIO_105) ERRORn2</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_ERROR2_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // ERROR1_N (GPIO_106) ERRORn1</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_ERROR1_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // ERROR0_N (GPIO_107) ERRORn0 Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_ERROR0_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // IERR_N (CATERR_N) (GPIO_108) IERRn (HardStrap Pull Up)</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_IERR_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // MCERR_N (GPIO_109) MCERR</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_MCERR_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB0_LEG_CLK (GPIO_110) LEG_SCL Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_SMB0_LEG_CLK, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB0_LEG_DATA (GPIO_111) LEG_SDA Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_SMB0_LEG_DATA, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB0_LEG_ALRT_N (GPIO_112) Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_SMB0_LEG_ALRT_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB1_HOST_DATA (GPIO_113) HOST_SDA Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+/*ME { SOUTH_GROUP0_SMB1_HOST_DATA, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },*/</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB1_HOST_CLK (GPIO_114) HOST_SCL Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+/*ME { SOUTH_GROUP0_SMB1_HOST_CLK, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },*/</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB2_PECI_DATA (GPIO_115) Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_SMB2_PECI_DATA, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB2_PECI_CLK (GPIO_116) Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_SMB2_PECI_CLK, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB4_CSME0_DATA (GPIO_117) ME_SDA Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+/*ME { SOUTH_GROUP0_SMB4_CSME0_DATA, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },*/</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB4_CSME0_CLK (GPIO_118) ME_SCL Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+/*ME { SOUTH_GROUP0_SMB4_CSME0_CLK, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },*/</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB4_CSME0_ALRT_N (GPIO_119) ME_ALRTn Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_SMB4_CSME0_ALRT_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // USB_OC0_N (GPIO_120) Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_USB_OC0_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // FLEX_CLK_SE0 (GPIO_121) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_FLEX_CLK_SE0, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // FLEX_CLK_SE1 (GPIO_122) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_FLEX_CLK_SE1, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // GBE3_LED1 (GPIO_4) LFFF: M2A_CFGn : M2A_SATAn, input</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_GPIO_4, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB3_IE0_CLK (GPIO_5) LFFF: M2B_CFGn : M2B_SATAn, input</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_GPIO_5, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB3_IE0_DATA (GPIO_6) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_GPIO_6, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB3_IE0_ALERT_N (GPIO_7) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_GPIO_7, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SATA0_LED (GPIO_90) SATA_LED0 Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_SATA0_LED_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SATA1_LED (GPIO_91) SATA_LED1 Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_SATA1_LED_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SATA_PDETECT0 (GPIO_92) Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_SATA_PDETECT0, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SATA_PDETECT1 (GPIO_93) Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_SATA_PDETECT1, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // UART1_RTS (GPIO_94) NC (Possible Pull Up)</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_SATA0_SDOUT, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // UART1_CTS (GPIO_95) NC (Possible Pull Up)</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_SATA1_SDOUT, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // UART1_RXD (GPIO_96) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_UART1_RXD, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // UART1_TXD (GPIO_97) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_UART1_TXD, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB6_CSME1_DATA (GPIO_8) LFFF: DVT_GPIO<1> : Baud select, input</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_GPIO_8, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB6_CSME1_CLK (GPIO_9) LFFF: DVT_GPIO<2> : Verbose Traces, input</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_GPIO_9, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // TCK (GPIO_141) n/a NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_TCK, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // TRST_N (GPIO_142) n/a NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_TRST_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // TMS (GPIO_143) n/a NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_TMS, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // TDI (GPIO_144) n/a NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_TDI, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // TDO (GPIO_145) n/a NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_TDO, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // CX_PRDY_N (GPIO_146) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_CX_PRDY_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // CX-PREQ_N (GPIO_147) Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_CX_PREQ_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // ME_RECVR_HDR (GPIO_148) ME_RECVR Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+/*ME { SOUTH_GROUP0_CTBTRIGINOUT, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },*/</span><br><span style="color: hsl(120, 100%, 40%);">+ // ADV_DBG_DFX_HDR (GPIO_149) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_CTBTRIGOUT, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // LAD2_SPI_IRQ_N (GPIO_150) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_DFX_SPARE2, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB_PECI_ALRT_N (GPIO_151) Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_DFX_SPARE3, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMB_CSME1_ALRT_N (GPIO_152) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP0_DFX_SPARE4, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SUSPWRDNACK (GPIO_79) SUSPWRDNACK Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_SUSPWRDNACK, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // PMU_SUSCLK (GPIO_80) PMU_SUSCLK</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_PMU_SUSCLK, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // ADR_TRIGGER_N (GPIO_81) Pull Down</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_ADR_TRIGGER, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // PMU_SLP_S45_N (GPIO_82) SLP_S45n</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_PMU_SLP_S45_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // PMU_SLP_S3_N (GPIO_83) SLP_S3n</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_PMU_SLP_S3_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // PMU_WAKE_N (GPIO_84) PMU_WAKEn Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_PMU_WAKE_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // PMU_PWRBTN_N (GPIO_85) PWNBTNn</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_PMU_PWRBTN_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // PMU_RESETBUTTON_N (GPIO_86) RSTBTNn</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_PMU_RESETBUTTON_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // PMU_PLTRST_N (GPIO_87) PLTRSTn</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_PMU_PLTRST_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // PMU_SUS_STAT_N (GPIO_88) SUS_STATn</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_SUS_STAT_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // TDB_CIO_PLUG_EVENT (GPIO_89) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_SLP_S0IX_N, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SPI_CS0_N (GPIO_72) SPI_CS0</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_SPI_CS0_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SPI_CS1_N (GPIO_73) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_SPI_CS1_N, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SPI_MOSI_IO0 (GPIO_74) SPI_MOSI</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_SPI_MOSI_IO0, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SPI_MISO_IO1 (GPIO_75) SPI_MISO</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_SPI_MISO_IO1, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SPI_IO2 (GPIO_76) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_SPI_IO2, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SPI_IO3 (GPIO_77) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_SPI_IO3, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // SPI_CLK (GPIO_78) SPI_CLK</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_SPI_CLK, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // LPC_AD0 (GPIO_64) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_ESPI_IO0, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // LPC_AD1 (GPIO_65) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_ESPI_IO1, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // LPC_AD2 (GPIO_66) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_ESPI_IO2, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // LPC_AD3 (GPIO_67) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_ESPI_IO3, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // LPC_FRAME_N (GPIO_68) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_ESPI_CS0_N, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // LPC_CLKOUT0 (GPIO_69) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_ESPI_CLK, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // LPC_CLKOUT1 (GPIO_70) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_ESPI_RST_N, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // LPC_CLKRUN_N (GPIO_71) Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_ESPI_ALRT0_N, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // MFG_MODE_HDR (GPIO_10) MFG_MODE Pull Up</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_GPIO_10, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirIn, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // LPC_SERIRQ (GPIO_11) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_GPIO_11, { GpioPadModeNative2, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // EMMC-CMD (GPIO_123) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_EMMC_CMD, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // EMMC-CSTROBE (GPIO_124) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_EMMC_STROBE, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // EMMC-CLK (GPIO_125) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_EMMC_CLK, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // EMMC-D0 (GPIO_126) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_EMMC_D0, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // EMMC-D1 (GPIO_127) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_EMMC_D1, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // EMMC-D2 (GPIO_128) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_EMMC_D2, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // EMMC-D3 (GPIO_129) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_EMMC_D3, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // EMMC-D4 (GPIO_130) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_EMMC_D4, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // EMMC-D5 (GPIO_131) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_EMMC_D5, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // EMMC-D6 (GPIO_132) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_EMMC_D6, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // EMMC-D7 (GPIO_133) NC</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_EMMC_D7, { GpioPadModeNative1, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermWpu20K, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+ // IE_ROM GPIO (GPIO_3) HS_TSO NC (Possible Pull Up)</span><br><span style="color: hsl(120, 100%, 40%);">+ { SOUTH_GROUP1_GPIO_3, { GpioPadModeGpio, GpioHostOwnGpio,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioDirOut, GpioOutDefault, GpioIntDefault, GpioResetPwrGood,</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioTermDefault, GpioPadConfigLock | GpioOutputStateLock } },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _MAINBOARD_GPIO_H */</span><br><span>diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..a8a2035</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/hsio.c</span><br><span>@@ -0,0 +1,26 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 - 2018 Online SAS.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <hsio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/fiamux.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t num;</span><br><span style="color: hsl(120, 100%, 40%);">+ num = ARRAY_SIZE(tagada_hsio_config);</span><br><span style="color: hsl(120, 100%, 40%);">+ (*p_hsio_config) = (BL_HSIO_INFORMATION *)tagada_hsio_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ return num;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/scaleway/tagada/hsio.h b/src/mainboard/scaleway/tagada/hsio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..e49fefd</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/hsio.h</span><br><span>@@ -0,0 +1,631 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016-2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 - 2018 Online SAS.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _MAINBOARD_HSIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define _MAINBOARD_HSIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __ACPI__</span><br><span style="color: hsl(120, 100%, 40%);">+const BL_HSIO_INFORMATION tagada_hsio_config[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Supported Lanes:</span><br><span style="color: hsl(120, 100%, 40%);">+ * 20</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Bifurcation:</span><br><span style="color: hsl(120, 100%, 40%);">+ * PCIE cluster #0: x4x4</span><br><span style="color: hsl(120, 100%, 40%);">+ * PCIE cluster #1: x2x2x2x2 (used for M2)</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * FIA MUX config:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Lane[00:03]-> disconnected</span><br><span style="color: hsl(120, 100%, 40%);">+ * Lane[08:11]-> 4 SATA side connectors</span><br><span style="color: hsl(120, 100%, 40%);">+ * Lane[12:15]-> 4 PCIe or 2 SATA (12,14) on M2 Connectors.</span><br><span style="color: hsl(120, 100%, 40%);">+ * M2 modules are detected; configuration updated by coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+ * Lane[19]->USB3 rear I/O panel connector</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SKU HSIO 20 (pcie [12-15] sata [8-11,12,14] usb [19]) */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_SKU_HSIO_20,</span><br><span style="color: hsl(120, 100%, 40%);">+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},</span><br><span style="color: hsl(120, 100%, 40%);">+ {/* ME_FIA_MUX_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME_FIA_SATA_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE07) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7)} } },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SKU HSIO 12 (pcie [12-15] sata [8-11,12,14] usb [19]) */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_SKU_HSIO_12,</span><br><span style="color: hsl(120, 100%, 40%);">+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},</span><br><span style="color: hsl(120, 100%, 40%);">+ {/* ME_FIA_MUX_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME_FIA_SATA_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE07) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG( BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7) |</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7)} } },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SKU HSIO 10 (pcie [12-15] sata [8-11,12,14] usb [19]) */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_SKU_HSIO_10,</span><br><span style="color: hsl(120, 100%, 40%);">+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},</span><br><span style="color: hsl(120, 100%, 40%);">+ {/* ME_FIA_MUX_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME_FIA_SATA_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE07) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7) |</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7)} } },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SKU HSIO 8 (pcie [12-14] sata [8-11,12,14] usb [19]) */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_SKU_HSIO_08,</span><br><span style="color: hsl(120, 100%, 40%);">+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},</span><br><span style="color: hsl(120, 100%, 40%);">+ {/* ME_FIA_MUX_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME_FIA_SATA_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE07) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7) |</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7)} } },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SKU HSIO 6 (pcie [12,14] sata [8-11,12,14] usb []) */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_SKU_HSIO_06,</span><br><span style="color: hsl(120, 100%, 40%);">+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},</span><br><span style="color: hsl(120, 100%, 40%);">+ {/* ME_FIA_MUX_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME_FIA_SATA_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE04) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE05) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE06) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE07) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE08) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE09) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE10) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_SATA_LANE19)},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */</span><br><span style="color: hsl(120, 100%, 40%);">+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7) |</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_3) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_6) |</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_CONFIG(</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_FIA_PCIE_ROOT_PORT_7)} } }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _MAINBOARD_HSIO_H */</span><br><span>diff --git a/src/mainboard/scaleway/tagada/ramstage.c b/src/mainboard/scaleway/tagada/ramstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..0aa6f13</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/ramstage.c</span><br><span>@@ -0,0 +1,26 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 - 2017 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 - 2018 Online SAS.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/api.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/ramstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_silicon_init_params(FSPS_UPD *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable eMMC */</span><br><span style="color: hsl(120, 100%, 40%);">+ params->FspsConfig.PcdEnableEmmc = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/scaleway/tagada/romstage.c b/src/mainboard/scaleway/tagada/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..d6a1282</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/romstage.c</span><br><span>@@ -0,0 +1,59 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 - 2018 Online SAS.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "gpio.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/api.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/soc_binding.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_config_gpios(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_memory_init_params(FSPM_UPD *mupd);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+* Configure GPIO depend on platform</span><br><span style="color: hsl(120, 100%, 40%);">+*/</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_config_gpios(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t num;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct pad_config *table;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Configure pads prior to SiliconInit() in case there's any</span><br><span style="color: hsl(120, 100%, 40%);">+ * dependencies during hardware initialization.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ table = tagada_gpio_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ num = ARRAY_SIZE(tagada_gpio_config);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((!table) || (!num)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "ERROR: No valid GPIO table found!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "GPIO table: 0x%x, entry num: 0x%x!\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ (uint32_t)table, (uint32_t)num);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_configure_pads(table, num);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_memory_init_params(FSPM_UPD *mupd)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ mupd->FspmConfig.PcdFspDebugPrintErrorLevel = 3; // Verbose</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Enable Rmt and Fast Boot by default, RMT will be run only on first</span><br><span style="color: hsl(120, 100%, 40%);">+ // boot or when dimms change</span><br><span style="color: hsl(120, 100%, 40%);">+ mupd->FspmConfig.PcdMrcRmtSupport = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ mupd->FspmConfig.PcdFastBoot = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23782">change 23782</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23782"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id4ecb760b9ab07ab168b252542dcaaea4636d655 </div>
<div style="display:none"> Gerrit-Change-Number: 23782 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert@online.net> </div>