[coreboot-gerrit] Change in coreboot[master]: soc/cavium: Clear LMC interrupt bits after CAR setup

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/23755


Change subject: soc/cavium: Clear LMC interrupt bits after CAR setup
......................................................................

soc/cavium: Clear LMC interrupt bits after CAR setup

Change-Id: I7b71eace5acb47eb42171cc4bfaf6fc1ff01df1c
Signed-off-by: Patrick Rudolph <patrick.rudolph at 9elements.com>
---
M src/soc/cavium/cn81xx/bootblock.c
M src/soc/cavium/cn81xx/bootblock_custom.S
2 files changed, 17 insertions(+), 22 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/23755/1

diff --git a/src/soc/cavium/cn81xx/bootblock.c b/src/soc/cavium/cn81xx/bootblock.c
index 9517fb7..2be7b6b 100644
--- a/src/soc/cavium/cn81xx/bootblock.c
+++ b/src/soc/cavium/cn81xx/bootblock.c
@@ -93,33 +93,11 @@
 void bootblock_soc_early_init(void)
 {
 
-	/* FIXME: will cache_sync_instructions() do? */
-	//cache_sync_instructions();
-
-	/* The above locking will cause L2 to load zeros without DRAM setup.
-	   This will cause L2C_TADX_INT[rddislmc].
-	   FIXME: Do we care? See bdk-init.c for reference code if so.
-	 */
 }
 
 
 void bootblock_soc_init(void)
 {
-#if 0
-            BDK_CSR_DEFINE(l2c_tadx_int, BDK_L2C_TADX_INT_W1C(0));
-            l2c_tadx_int.u = 0;
-            l2c_tadx_int.s.wrdislmc = 1;
-            l2c_tadx_int.s.rddislmc = 1;
-            l2c_tadx_int.s.rdnxm = 1;
-
-            BDK_CSR_WRITE(node, BDK_L2C_TADX_INT_W1C(0), l2c_tadx_int.u);
-#endif
-	struct cn81xx_l2c_tad *tad = (struct cn81xx_l2c_tad *)L2C_TAD0_PF_BAR0;
-	write64(&tad->int_w1c, L2C_TAD_INT_W1C_WRDISLMC |
-			L2C_TAD_INT_W1C_RDDISLMC | L2C_TAD_INT_W1C_RDNXM);
-
-	/* FIXME: additional locking steps required for CN88xx and CN83xx */
-
 	/* initialize system registers */
 	init_sysreg();
 
diff --git a/src/soc/cavium/cn81xx/bootblock_custom.S b/src/soc/cavium/cn81xx/bootblock_custom.S
index 00a6aff..fab2e43 100644
--- a/src/soc/cavium/cn81xx/bootblock_custom.S
+++ b/src/soc/cavium/cn81xx/bootblock_custom.S
@@ -227,6 +227,23 @@
     b.gt    dirty_cache_line    /* Repeat if length is still positive */
     dmb     sy
 
+clear_interrupts:
+    /**
+     * As the memory controller isn't running, but we access the DRAM's
+     * address space, some interrupt flags had been set.
+     * Tidy up our mess now on (valid for CN81XX only).
+     */
+    #define L2C_TAD0_INT_W1C 0x87e050040000ULL
+    mov     x0, (L2C_TAD0_INT_W1C >> 32)
+    lsl     x0, x0, 32
+    mov     x1, (L2C_TAD0_INT_W1C & 0xffffffff)
+    orr     x0, x0, x1
+    #undef L2C_TAD0_INT_W1C
+
+    ldr x1, [x0]
+    orr x1, x1, 0x1c00 /* Clear WRDISLMC, RDDISLMC, RDNXM */
+    str x1, [x0]
+
     ret
 ENDPROC(_setup_car)
 

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7b71eace5acb47eb42171cc4bfaf6fc1ff01df1c
Gerrit-Change-Number: 23755
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph at 9elements.com>
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