<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23755">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/cavium: Clear LMC interrupt bits after CAR setup<br><br>Change-Id: I7b71eace5acb47eb42171cc4bfaf6fc1ff01df1c<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>---<br>M src/soc/cavium/cn81xx/bootblock.c<br>M src/soc/cavium/cn81xx/bootblock_custom.S<br>2 files changed, 17 insertions(+), 22 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/23755/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/cavium/cn81xx/bootblock.c b/src/soc/cavium/cn81xx/bootblock.c</span><br><span>index 9517fb7..2be7b6b 100644</span><br><span>--- a/src/soc/cavium/cn81xx/bootblock.c</span><br><span>+++ b/src/soc/cavium/cn81xx/bootblock.c</span><br><span>@@ -93,33 +93,11 @@</span><br><span> void bootblock_soc_early_init(void)</span><br><span> {</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* FIXME: will cache_sync_instructions() do? */</span><br><span style="color: hsl(0, 100%, 40%);">- //cache_sync_instructions();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* The above locking will cause L2 to load zeros without DRAM setup.</span><br><span style="color: hsl(0, 100%, 40%);">- This will cause L2C_TADX_INT[rddislmc].</span><br><span style="color: hsl(0, 100%, 40%);">- FIXME: Do we care? See bdk-init.c for reference code if so.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span> }</span><br><span> </span><br><span> </span><br><span> void bootblock_soc_init(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">- BDK_CSR_DEFINE(l2c_tadx_int, BDK_L2C_TADX_INT_W1C(0));</span><br><span style="color: hsl(0, 100%, 40%);">- l2c_tadx_int.u = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- l2c_tadx_int.s.wrdislmc = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- l2c_tadx_int.s.rddislmc = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- l2c_tadx_int.s.rdnxm = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- BDK_CSR_WRITE(node, BDK_L2C_TADX_INT_W1C(0), l2c_tadx_int.u);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">- struct cn81xx_l2c_tad *tad = (struct cn81xx_l2c_tad *)L2C_TAD0_PF_BAR0;</span><br><span style="color: hsl(0, 100%, 40%);">- write64(&tad->int_w1c, L2C_TAD_INT_W1C_WRDISLMC |</span><br><span style="color: hsl(0, 100%, 40%);">- L2C_TAD_INT_W1C_RDDISLMC | L2C_TAD_INT_W1C_RDNXM);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* FIXME: additional locking steps required for CN88xx and CN83xx */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* initialize system registers */</span><br><span> init_sysreg();</span><br><span> </span><br><span>diff --git a/src/soc/cavium/cn81xx/bootblock_custom.S b/src/soc/cavium/cn81xx/bootblock_custom.S</span><br><span>index 00a6aff..fab2e43 100644</span><br><span>--- a/src/soc/cavium/cn81xx/bootblock_custom.S</span><br><span>+++ b/src/soc/cavium/cn81xx/bootblock_custom.S</span><br><span>@@ -227,6 +227,23 @@</span><br><span> b.gt dirty_cache_line /* Repeat if length is still positive */</span><br><span> dmb sy</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+clear_interrupts:</span><br><span style="color: hsl(120, 100%, 40%);">+ /**</span><br><span style="color: hsl(120, 100%, 40%);">+ * As the memory controller isn't running, but we access the DRAM's</span><br><span style="color: hsl(120, 100%, 40%);">+ * address space, some interrupt flags had been set.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Tidy up our mess now on (valid for CN81XX only).</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ #define L2C_TAD0_INT_W1C 0x87e050040000ULL</span><br><span style="color: hsl(120, 100%, 40%);">+ mov x0, (L2C_TAD0_INT_W1C >> 32)</span><br><span style="color: hsl(120, 100%, 40%);">+ lsl x0, x0, 32</span><br><span style="color: hsl(120, 100%, 40%);">+ mov x1, (L2C_TAD0_INT_W1C & 0xffffffff)</span><br><span style="color: hsl(120, 100%, 40%);">+ orr x0, x0, x1</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef L2C_TAD0_INT_W1C</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ldr x1, [x0]</span><br><span style="color: hsl(120, 100%, 40%);">+ orr x1, x1, 0x1c00 /* Clear WRDISLMC, RDDISLMC, RDNXM */</span><br><span style="color: hsl(120, 100%, 40%);">+ str x1, [x0]</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> ret</span><br><span> ENDPROC(_setup_car)</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23755">change 23755</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7b71eace5acb47eb42171cc4bfaf6fc1ff01df1c </div>
<div style="display:none"> Gerrit-Change-Number: 23755 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>