[coreboot-gerrit] Change in coreboot[master]: arch/riscv: Make RVC support configurable

[Jonathan Neuschäfer (Code Review)]

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/23733


Change subject: arch/riscv: Make RVC support configurable
......................................................................

arch/riscv: Make RVC support configurable

In order to support RISC-V processors with and without the RVC
extension, configure the architecture variant (-march=...) explicitly.

NOTE: Spike does support RVC, but currently doesn't select
      ARCH_RISCV_COMPRESSED, because coreboot's trap handler doesn't
      support RVC.

Change-Id: Id4f69fa6b33604a5aa60fd6f6da8bd966494112f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
M src/arch/riscv/Kconfig
M src/arch/riscv/Makefile.inc
2 files changed, 20 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/23733/1

diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index a30cb70..2513c50 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -2,6 +2,13 @@
 	bool
 	default n
 
+config ARCH_RISCV_COMPRESSED
+	bool
+	default n
+	help
+	  Enable this option if your RISC-V processor supports compressed
+	  instructions (RVC). Currently, this enables RVC for all stages.
+
 config ARCH_BOOTBLOCK_RISCV
 	bool
 	default n
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index d2b6cce..4b2ff03 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -15,14 +15,24 @@
 ##
 ################################################################################
 
-riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany
-
-riscv_asm_flags =
+################################################################################
+## RISC-V specific options
+################################################################################
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
 check-ramstage-overlap-regions += stack
 endif
 
+riscv_arch = rv64imafd
+
+ifeq ($(CONFIG_ARCH_RISCV_COMPRESSED),y)
+	riscv_arch := $(riscv_arch)c
+endif
+
+riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany -march=$(riscv_arch)
+
+riscv_asm_flags = -march=$(riscv_arch)
+
 ################################################################################
 ## bootblock
 ################################################################################

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id4f69fa6b33604a5aa60fd6f6da8bd966494112f
Gerrit-Change-Number: 23733
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
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