<p>Jonathan Neuschäfer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23733">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">arch/riscv: Make RVC support configurable<br><br>In order to support RISC-V processors with and without the RVC<br>extension, configure the architecture variant (-march=...) explicitly.<br><br>NOTE: Spike does support RVC, but currently doesn't select<br> ARCH_RISCV_COMPRESSED, because coreboot's trap handler doesn't<br> support RVC.<br><br>Change-Id: Id4f69fa6b33604a5aa60fd6f6da8bd966494112f<br>Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net><br>---<br>M src/arch/riscv/Kconfig<br>M src/arch/riscv/Makefile.inc<br>2 files changed, 20 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/23733/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig</span><br><span>index a30cb70..2513c50 100644</span><br><span>--- a/src/arch/riscv/Kconfig</span><br><span>+++ b/src/arch/riscv/Kconfig</span><br><span>@@ -2,6 +2,13 @@</span><br><span> bool</span><br><span> default n</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config ARCH_RISCV_COMPRESSED</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable this option if your RISC-V processor supports compressed</span><br><span style="color: hsl(120, 100%, 40%);">+ instructions (RVC). Currently, this enables RVC for all stages.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config ARCH_BOOTBLOCK_RISCV</span><br><span> bool</span><br><span> default n</span><br><span>diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc</span><br><span>index d2b6cce..4b2ff03 100644</span><br><span>--- a/src/arch/riscv/Makefile.inc</span><br><span>+++ b/src/arch/riscv/Makefile.inc</span><br><span>@@ -15,14 +15,24 @@</span><br><span> ##</span><br><span> ################################################################################</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-riscv_asm_flags =</span><br><span style="color: hsl(120, 100%, 40%);">+################################################################################</span><br><span style="color: hsl(120, 100%, 40%);">+## RISC-V specific options</span><br><span style="color: hsl(120, 100%, 40%);">+################################################################################</span><br><span> </span><br><span> ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)</span><br><span> check-ramstage-overlap-regions += stack</span><br><span> endif</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+riscv_arch = rv64imafd</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ifeq ($(CONFIG_ARCH_RISCV_COMPRESSED),y)</span><br><span style="color: hsl(120, 100%, 40%);">+ riscv_arch := $(riscv_arch)c</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany -march=$(riscv_arch)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+riscv_asm_flags = -march=$(riscv_arch)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> ################################################################################</span><br><span> ## bootblock</span><br><span> ################################################################################</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23733">change 23733</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23733"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id4f69fa6b33604a5aa60fd6f6da8bd966494112f </div>
<div style="display:none"> Gerrit-Change-Number: 23733 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer@gmx.net> </div>