[coreboot-gerrit] Change in coreboot[master]: src/soc: Fix various typos
Jonathan Neuschäfer (Code Review)
gerrit at coreboot.org
Mon Feb 12 12:52:31 CET 2018
Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/23706
Change subject: src/soc: Fix various typos
......................................................................
src/soc: Fix various typos
These typos were found through manual review and grep.
Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
M src/soc/amd/stoneyridge/include/soc/northbridge.h
M src/soc/amd/stoneyridge/southbridge.c
M src/soc/broadcom/cygnus/hw_init.c
M src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h
M src/soc/imgtec/pistachio/ddr2_init.c
M src/soc/imgtec/pistachio/ddr3_init.c
M src/soc/intel/apollolake/include/soc/meminit.h
M src/soc/intel/apollolake/meminit.c
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/apollolake/systemagent.c
M src/soc/intel/cannonlake/include/soc/bootblock.h
M src/soc/intel/cannonlake/include/soc/vr_config.h
M src/soc/intel/cannonlake/romstage/systemagent.c
M src/soc/intel/cannonlake/systemagent.c
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/include/intelblocks/acpi.h
M src/soc/intel/common/block/include/intelblocks/lpc_lib.h
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/include/intelblocks/systemagent.h
M src/soc/intel/common/block/pcr/pcr.c
M src/soc/intel/common/block/pmc/pmclib.c
M src/soc/intel/common/block/sgx/Kconfig
M src/soc/intel/common/block/sgx/sgx.c
M src/soc/intel/common/block/systemagent/systemagent_def.h
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/denverton_ns/bootblock/uart.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/gpio.c
M src/soc/intel/denverton_ns/include/soc/bootblock.h
M src/soc/intel/denverton_ns/include/soc/gpio_defs.h
M src/soc/intel/denverton_ns/include/soc/smm.h
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/skylake/include/soc/bootblock.h
M src/soc/intel/skylake/include/soc/vr_config.h
M src/soc/intel/skylake/irq.c
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/romstage/systemagent.c
M src/soc/intel/skylake/systemagent.c
M src/soc/marvell/mvmap2315/pmic.c
M src/soc/nvidia/tegra210/romstage.c
M src/soc/qualcomm/ipq40xx/blobs_init.c
M src/soc/qualcomm/ipq806x/blobs_init.c
44 files changed, 82 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/23706/1
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index b0bbd54..d649ada 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -80,7 +80,7 @@
void smm_region_info(void **start, size_t *size);
/*
* Fills in the start and size for the requested SMM subregion. Returns
- * 0 on susccess, < 0 on failure.
+ * 0 on success, < 0 on failure.
*/
int smm_subregion(int sub, void **start, size_t *size);
void domain_enable_resources(device_t dev);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 735642f..100d4e6 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -75,7 +75,7 @@
/*
* Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME
- * provides a visible association with the index, therefor helping
+ * provides a visible association with the index, therefore helping
* maintainability of table. If a new index/name is defined in
* amd_pci_int_defs.h, just add the pair at the end of this table.
* Order is not important.
diff --git a/src/soc/broadcom/cygnus/hw_init.c b/src/soc/broadcom/cygnus/hw_init.c
index b9e5857..ce5592f 100644
--- a/src/soc/broadcom/cygnus/hw_init.c
+++ b/src/soc/broadcom/cygnus/hw_init.c
@@ -106,7 +106,7 @@
*
* NOTE: In the future, we might want to protect particular CRMU
* sub-blocks to allow SECURE access only. That can be done by
- * programing the CRMU IPROC address range registers. Up to 4 access
+ * programming the CRMU IPROC address range registers. Up to 4 access
* windows can be created
*/
write32((void *)CRMU_IPROC_ADDR_RANGE0_LOW,
diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h
index 166cc0b..93489bb 100644
--- a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h
+++ b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h
@@ -218,7 +218,7 @@
#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC 0x000004a0 /* Read enable bit-clock cycle delay control register */
#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC 0x000004a4 /* Write leveling bit-clock cycle delay control register */
#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL 0x000004b0 /* Read channel datapath control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR 0x000004b4 /* Read fifo addresss pointer register */
+#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR 0x000004b4 /* Read fifo address pointer register */
#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DATA 0x000004b8 /* Read fifo data register */
#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI 0x000004bc /* Read fifo dm/dbi register */
#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS 0x000004c0 /* Read fifo status register */
@@ -284,7 +284,7 @@
#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC 0x000006a0 /* Read enable bit-clock cycle delay control register */
#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC 0x000006a4 /* Write leveling bit-clock cycle delay control register */
#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL 0x000006b0 /* Read channel datapath control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR 0x000006b4 /* Read fifo addresss pointer register */
+#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR 0x000006b4 /* Read fifo address pointer register */
#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DATA 0x000006b8 /* Read fifo data register */
#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI 0x000006bc /* Read fifo dm/dbi register */
#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS 0x000006c0 /* Read fifo status register */
@@ -7729,7 +7729,7 @@
#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
+ *READ_FIFO_ADDR - Read fifo address pointer register
***************************************************************************/
/* DDR34_CORE_PHY_BYTE_LANE_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
@@ -10483,7 +10483,7 @@
#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
/***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
+ *READ_FIFO_ADDR - Read fifo address pointer register
***************************************************************************/
/* DDR34_CORE_PHY_BYTE_LANE_1 :: READ_FIFO_ADDR :: reserved0 [31:03] */
#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c
index 9549537..aac85a9 100644
--- a/src/soc/imgtec/pistachio/ddr2_init.c
+++ b/src/soc/imgtec/pistachio/ddr2_init.c
@@ -288,7 +288,7 @@
*/
write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x00000012);
/*
- * TRC : Min. ROW cylce time
+ * TRC : Min. ROW cycle time
* Range 11 to 31: 57.5ns / 2.5ns = 23d Playing safe 24
*/
write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000018);
diff --git a/src/soc/imgtec/pistachio/ddr3_init.c b/src/soc/imgtec/pistachio/ddr3_init.c
index 5cb36a0..b3f723c 100644
--- a/src/soc/imgtec/pistachio/ddr3_init.c
+++ b/src/soc/imgtec/pistachio/ddr3_init.c
@@ -303,7 +303,7 @@
write32(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005);
/* TRAS : Activate to Precharge cmd time 15 45ns / 2.5ns = 18d */
write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x0000000F);
- /* TRC : Min. ROW cylce time 21
+ /* TRC : Min. ROW cycle time 21
* 57.5ns / 2.5ns = 23d Playing safe 24
*/
write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000015);
@@ -428,7 +428,7 @@
*/
write32(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x060600000);
- /* Memory initilization */
+ /* Memory initialization */
/* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0
* 3:0 cmd_opcode PREA 00001
* 16:4 cmd_addr 0
diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h
index 339d2b1..fa12728 100644
--- a/src/soc/intel/apollolake/include/soc/meminit.h
+++ b/src/soc/intel/apollolake/include/soc/meminit.h
@@ -76,7 +76,7 @@
* and LOW for ODT_B, choose ODT_AB_HIGH_LOW.
*
* Note that the enum values correspond to the interpreted UPD fields
- * witihn Ch[3:0]_OdtConfig parameters.
+ * within Ch[3:0]_OdtConfig parameters.
*/
enum {
ODT_A_B_HIGH_LOW = 0 << 1,
diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c
index 91cdeb5..dd8b591 100644
--- a/src/soc/intel/apollolake/meminit.c
+++ b/src/soc/intel/apollolake/meminit.c
@@ -130,10 +130,10 @@
/*
* CH0_DQB byte lanes in the bit swizzle configuration field are
* not 1:1. The mapping within the swizzling field is:
- * indicies [0:7] - byte lane 1 (DQS1) DQ[8:15]
- * indicies [8:15] - byte lane 0 (DQS0) DQ[0:7]
- * indicies [16:23] - byte lane 3 (DQS3) DQ[24:31]
- * indicies [24:31] - byte lane 2 (DQS2) DQ[16:23]
+ * indices [0:7] - byte lane 1 (DQS1) DQ[8:15]
+ * indices [8:15] - byte lane 0 (DQS0) DQ[0:7]
+ * indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
+ * indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
*/
chan = &scfg->phys[LP4_PHYS_CH0B];
memcpy(&cfg->Ch0_Bit_swizzling[0], &chan->dqs[LP4_DQS1], sz);
@@ -175,10 +175,10 @@
/*
* CH1_DQB byte lanes in the bit swizzle configuration field are
* not 1:1. The mapping within the swizzling field is:
- * indicies [0:7] - byte lane 1 (DQS1) DQ[8:15]
- * indicies [8:15] - byte lane 0 (DQS0) DQ[0:7]
- * indicies [16:23] - byte lane 3 (DQS3) DQ[24:31]
- * indicies [24:31] - byte lane 2 (DQS2) DQ[16:23]
+ * indices [0:7] - byte lane 1 (DQS1) DQ[8:15]
+ * indices [8:15] - byte lane 0 (DQS0) DQ[0:7]
+ * indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
+ * indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
*/
chan = &scfg->phys[LP4_PHYS_CH1B];
memcpy(&cfg->Ch2_Bit_swizzling[0], &chan->dqs[LP4_DQS1], sz);
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 20b67fd..1db2982 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -87,7 +87,7 @@
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
};
- /* Set Fixed MMIO addresss into PCI configuration space */
+ /* Set Fixed MMIO address into PCI configuration space */
sa_set_pci_bar(soc_fixed_pci_resources,
ARRAY_SIZE(soc_fixed_pci_resources));
diff --git a/src/soc/intel/apollolake/systemagent.c b/src/soc/intel/apollolake/systemagent.c
index 57de4b8..c8f1330 100644
--- a/src/soc/intel/apollolake/systemagent.c
+++ b/src/soc/intel/apollolake/systemagent.c
@@ -27,7 +27,7 @@
/*
* SoC implementation
*
- * Add all known fixed memory ranges for Host Controller/Mmeory
+ * Add all known fixed memory ranges for Host Controller/Memory
* controller.
*/
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
diff --git a/src/soc/intel/cannonlake/include/soc/bootblock.h b/src/soc/intel/cannonlake/include/soc/bootblock.h
index 2a6ca1f..a5c3c32 100644
--- a/src/soc/intel/cannonlake/include/soc/bootblock.h
+++ b/src/soc/intel/cannonlake/include/soc/bootblock.h
@@ -18,11 +18,11 @@
#include <intelblocks/systemagent.h>
-/* Bootblock pre console init programing */
+/* Bootblock pre console init programming */
void bootblock_cpu_init(void);
void bootblock_pch_early_init(void);
-/* Bootblock post console init programing */
+/* Bootblock post console init programming */
void pch_early_init(void);
void pch_early_iorange_init(void);
void report_platform_info(void);
diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h
index 2cd7dd9..385767d 100644
--- a/src/soc/intel/cannonlake/include/soc/vr_config.h
+++ b/src/soc/intel/cannonlake/include/soc/vr_config.h
@@ -26,7 +26,7 @@
* for that domain. */
uint8_t vr_config_enable;
- /* Power State X current cuttof in 1/4 Amp increments
+ /* Power State X current cutoff in 1/4 Amp increments
* Range is 0-128A */
uint16_t psi1threshold;
uint16_t psi2threshold;
diff --git a/src/soc/intel/cannonlake/romstage/systemagent.c b/src/soc/intel/cannonlake/romstage/systemagent.c
index f7c7f1a..61db22e 100644
--- a/src/soc/intel/cannonlake/romstage/systemagent.c
+++ b/src/soc/intel/cannonlake/romstage/systemagent.c
@@ -34,12 +34,12 @@
{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
};
- /* Set Fixed MMIO addresss into PCI configuration space */
+ /* Set Fixed MMIO address into PCI configuration space */
sa_set_pci_bar(soc_fixed_pci_resources,
ARRAY_SIZE(soc_fixed_pci_resources));
- /* Set Fixed MMIO addresss into MCH base address */
+ /* Set Fixed MMIO address into MCH base address */
sa_set_mch_bar(soc_fixed_mch_resources,
ARRAY_SIZE(soc_fixed_mch_resources));
- /* Enable PAM regisers */
+ /* Enable PAM registers */
enable_pam_region();
}
diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c
index 344517d..06b37e0 100644
--- a/src/soc/intel/cannonlake/systemagent.c
+++ b/src/soc/intel/cannonlake/systemagent.c
@@ -25,7 +25,7 @@
/*
* SoC implementation
*
- * Add all known fixed memory ranges for Host Controller/Mmeory
+ * Add all known fixed memory ranges for Host Controller/Memory
* controller.
*/
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 1798de5..02aeefe 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -389,7 +389,7 @@
* Maximizing RO cacheability while locking in the CAR to a
* single way since that particular way won't be victim candidate
* for evictions.
- * This has been done after programing LLC_WAY_MASK_1 MSR
+ * This has been done after programming LLC_WAY_MASK_1 MSR
* with desired LLC way as mentioned below.
*
* Hence create Code and Data Size as per request
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 0ff999e..4991db6 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -31,7 +31,7 @@
/* Wait up to 15 sec for HECI to get ready */
#define HECI_DELAY_READY (15 * 1000)
-/* Wait up to 100 usec between circullar buffer polls */
+/* Wait up to 100 usec between circular buffer polls */
#define HECI_DELAY 100
/* Wait up to 5 sec for CSE to chew something we sent */
#define HECI_SEND_TIMEOUT (5 * 1000)
@@ -126,7 +126,7 @@
static uint32_t read_bar(uint32_t offset)
{
struct cse_device *cse = car_get_var_ptr(&g_cse);
- /* Reach PCI config space to get BAR incase CAR global not available */
+ /* Reach PCI config space to get BAR in case CAR global not available */
if (!cse->sec_bar)
cse->sec_bar = get_cse_bar();
return read32((void *)(cse->sec_bar + offset));
@@ -135,7 +135,7 @@
static void write_bar(uint32_t offset, uint32_t val)
{
struct cse_device *cse = car_get_var_ptr(&g_cse);
- /* Reach PCI config space to get BAR incase CAR global not available */
+ /* Reach PCI config space to get BAR in case CAR global not available */
if (!cse->sec_bar)
cse->sec_bar = get_cse_bar();
return write32((void *)(cse->sec_bar + offset), val);
@@ -341,7 +341,7 @@
/*
* Fragment the message into smaller messages not exceeding
- * useful circullar buffer length. Mark last message complete.
+ * useful circular buffer length. Mark last message complete.
*/
do {
hdr = MIN(max_length, remaining)
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 5b2527c..dcf8200 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -24,7 +24,7 @@
__attribute__((weak)) void graphics_soc_init(struct device *dev)
{
/*
- * User needs to implement SoC override incase wishes
+ * User needs to implement SoC override in case wishes
* to perform certain specific graphics initialization
* along with pci_dev_init(dev)
*/
diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h
index 73a9c9c..927da3c 100644
--- a/src/soc/intel/common/block/include/intelblocks/acpi.h
+++ b/src/soc/intel/common/block/include/intelblocks/acpi.h
@@ -44,7 +44,7 @@
struct acpi_rsdp *rsdp);
/*
- * Craetes acpi gnvs and adds it to the DSDT table.
+ * Creates acpi gnvs and adds it to the DSDT table.
* GNVS creation is chipset specific and is done in soc specific acpi.c file.
*/
void southbridge_inject_dsdt(device_t device);
@@ -84,7 +84,7 @@
/*
* soc specific power states generation. We need this to be defined by soc
* as the state generations varies in chipsets e.g. APL generates T and P
- * states while SKL generates * P state only depening on a devicetree config
+ * states while SKL generates * P state only depending on a devicetree config
*/
void soc_power_states_generation(int core_id, int cores_per_package);
diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
index 554c75d..7269bef 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
@@ -69,14 +69,14 @@
void lpc_open_mmio_window(uintptr_t base, size_t size);
/* Returns true if given window is decoded to LPC via a fixed range. */
bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size);
-/* Init SoC Spcific LPC features. Common definition will be weak and
+/* Init SoC Specific LPC features. Common definition will be weak and
each soc will need to define the init. */
void lpc_soc_init(struct device *dev);
/* Fill up LPC IO resource structure inside SoC directory */
void pch_lpc_soc_fill_io_resources(struct device *dev);
/* Init LPC GPIO pads */
void lpc_configure_pads(void);
-/* Get SoC speicific MMIO ranges */
+/* Get SoC specific MMIO ranges */
const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void);
/* Set LPC BIOS Control BILD bit. */
void lpc_set_bios_interface_lock_down(void);
@@ -97,7 +97,7 @@
void lpc_io_setup_comm_a_b(void);
/* Enable PCH LPC by setting up generic decode range registers. */
void pch_enable_lpc(void);
-/* Retrieve and setup SoC speicific PCH LPC interrupt routing. */
+/* Retrieve and setup SoC specific PCH LPC interrupt routing. */
void soc_pch_pirq_init(const struct device *dev);
/* Get SoC's generic IO decoder range register settings. */
void soc_get_gen_io_dec_range(const struct device *dev,
diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h
index 3827cf5..d631f01 100644
--- a/src/soc/intel/common/block/include/intelblocks/pmclib.h
+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h
@@ -37,7 +37,7 @@
/*
* This function is specific to soc and is defined as weak in common
* pmclib file. SOC code can implement it for any special condition
- * specific to the soc e.g. in SKL in handles deep S3 scenerio.
+ * specific to the soc e.g. in SKL in handles deep S3 scenario.
* Return ACPI_SX values to indicate the previous sleep state.
*/
int soc_prev_sleep_state(const struct chipset_power_state *ps,
@@ -206,7 +206,7 @@
void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2);
/*
- * Reads soc specific power management crtitical registers, fills
+ * Reads soc specific power management critical registers, fills
* chipset_power_state structure variable and prints.
*/
void soc_fill_power_state(struct chipset_power_state *ps);
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
index 64b2c36..a731b9c 100644
--- a/src/soc/intel/common/block/include/intelblocks/systemagent.h
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -52,10 +52,10 @@
const char *description;
};
-/* API to set Fixed MMIO addresss into PCI configuration space */
+/* API to set Fixed MMIO address into PCI configuration space */
void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources,
size_t count);
-/* API to set Fixed MMIO addresss into MCH base address */
+/* API to set Fixed MMIO address into MCH base address */
void sa_set_mch_bar(const struct sa_mmio_descriptor *fixed_set_resources,
size_t count);
/*
@@ -69,7 +69,7 @@
* SoC to provide BIOS_RESET_CPL register offset through soc/systemagent.h
*/
void enable_bios_reset_cpl(void);
-/* API to enable PAM regisers */
+/* API to enable PAM registers */
void enable_pam_region(void);
/* API to enable Power Aware Interrupt Routing through MCHBAR */
void enable_power_aware_intr(void);
diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c
index 4264cdf..e106c41 100644
--- a/src/soc/intel/common/block/pcr/pcr.c
+++ b/src/soc/intel/common/block/pcr/pcr.c
@@ -59,7 +59,7 @@
uint32_t pcr_read32(uint8_t pid, uint16_t offset)
{
- /* Ensure the PCR offset is corretcly aligned. */
+ /* Ensure the PCR offset is correctly aligned. */
assert(IS_ALIGNED(offset, sizeof(uint32_t)));
return read32(__pcr_reg_address(pid, offset));
@@ -67,7 +67,7 @@
uint16_t pcr_read16(uint8_t pid, uint16_t offset)
{
- /* Ensure the PCR offset is corretcly aligned. */
+ /* Ensure the PCR offset is correctly aligned. */
check_pcr_offset_align(offset, sizeof(uint16_t));
return read16(__pcr_reg_address(pid, offset));
@@ -75,7 +75,7 @@
uint8_t pcr_read8(uint8_t pid, uint16_t offset)
{
- /* Ensure the PCR offset is corretcly aligned. */
+ /* Ensure the PCR offset is correctly aligned. */
check_pcr_offset_align(offset, sizeof(uint8_t));
return read8(__pcr_reg_address(pid, offset));
@@ -94,7 +94,7 @@
void pcr_write32(uint8_t pid, uint16_t offset, uint32_t indata)
{
- /* Ensure the PCR offset is corretcly aligned. */
+ /* Ensure the PCR offset is correctly aligned. */
assert(IS_ALIGNED(offset, sizeof(indata)));
write32(__pcr_reg_address(pid, offset), indata);
@@ -104,7 +104,7 @@
void pcr_write16(uint8_t pid, uint16_t offset, uint16_t indata)
{
- /* Ensure the PCR offset is corretcly aligned. */
+ /* Ensure the PCR offset is correctly aligned. */
check_pcr_offset_align(offset, sizeof(uint16_t));
write16(__pcr_reg_address(pid, offset), indata);
@@ -114,7 +114,7 @@
void pcr_write8(uint8_t pid, uint16_t offset, uint8_t indata)
{
- /* Ensure the PCR offset is corretcly aligned. */
+ /* Ensure the PCR offset is correctly aligned. */
check_pcr_offset_align(offset, sizeof(uint8_t));
write8(__pcr_reg_address(pid, offset), indata);
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index dea7e1b..cf87d05 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -360,7 +360,7 @@
/*
* Returns prev_sleep_state and also prints all power management registers.
- * Calls soc_prev_sleep_state which may be impelmented by SOC.
+ * Calls soc_prev_sleep_state which may be implemented by SOC.
*/
static int pmc_prev_sleep_state(const struct chipset_power_state *ps)
{
diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig
index 7889582..0852bfb 100644
--- a/src/soc/intel/common/block/sgx/Kconfig
+++ b/src/soc/intel/common/block/sgx/Kconfig
@@ -3,5 +3,5 @@
default n
help
Software Guard eXtension(SGX) Feature. Intel SGX is a set of new CPU
- instructions that can be used by applications to set aside privat
+ instructions that can be used by applications to set aside private
regions of code and data.
diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c
index 86789fa..d3be15c 100644
--- a/src/soc/intel/common/block/sgx/sgx.c
+++ b/src/soc/intel/common/block/sgx/sgx.c
@@ -193,11 +193,11 @@
msr_t msr;
msr = rdmsr(PRMRR_PHYS_MASK_MSR);
if (msr.lo & PRMRR_PHYS_MASK_VALID) {
- printk(BIOS_INFO, "SGX: MCHECK aprroved SGX PRMRR\n");
+ printk(BIOS_INFO, "SGX: MCHECK approved SGX PRMRR\n");
return 1;
}
- printk(BIOS_INFO, "SGX: MCHECK did not aprrove SGX PRMRR\n");
+ printk(BIOS_INFO, "SGX: MCHECK did not approve SGX PRMRR\n");
return 0;
}
@@ -226,7 +226,7 @@
/* Lock the SGX feature */
lock_sgx();
- /* Activate the SGX feature, if PRMRR config was aprroved by MCHECK */
+ /* Activate the SGX feature, if PRMRR config was approved by MCHECK */
if (is_prmrr_approved())
activate_sgx();
}
diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h
index e028692..b89a10d 100644
--- a/src/soc/intel/common/block/systemagent/systemagent_def.h
+++ b/src/soc/intel/common/block/systemagent/systemagent_def.h
@@ -19,13 +19,13 @@
/* Device 0:0.0 PCI configuration space */
-/* GMCH Graphics Comntrol Register */
+/* GMCH Graphics Control Register */
#define GGC 0x50
#define G_GMS_OFFSET 0x8
#define G_GMS_MASK 0xff00
#define G_GGMS_OFFSET 0x6
#define G_GGMS_MASK 0xc0
-/* DPR register incase CONFIG_SA_ENABLE_DPR is selected by SoC */
+/* DPR register in case CONFIG_SA_ENABLE_DPR is selected by SoC */
#define DPR 0x5c
#define DPR_EPM (1 << 2)
#define DPR_PRS (1 << 1)
@@ -48,7 +48,7 @@
#define MCH_PAIR 0x5418
/*
- * IMR register incase CONFIG_SA_ENABLE_IMR is selected by SoC.
+ * IMR register in case CONFIG_SA_ENABLE_IMR is selected by SoC.
*
* IMR registers are found under MCHBAR.
*/
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 91badc7..9f26ef1 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -106,7 +106,7 @@
static bool uart_controller_needs_init(struct device *dev)
{
/*
- * If coreboot has CONSOLE_SERIAL enabled, the skip re-initalizing
+ * If coreboot has CONSOLE_SERIAL enabled, the skip re-initializing
* controller here.
*/
if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c
index a81b389..affddba 100644
--- a/src/soc/intel/denverton_ns/bootblock/uart.c
+++ b/src/soc/intel/denverton_ns/bootblock/uart.c
@@ -185,7 +185,7 @@
{
register int i;
- /* Check: do we have enought elements to init. ? */
+ /* Check: do we have enough elements to init. ? */
BUILD_BUG_ON(DENVERTON_UARTS_TO_INI > ELEM_OF_UART_TAB);
/* HSUART(B0:D26:0-1) GPIO init. */
diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c
index 7848883..7de0976 100644
--- a/src/soc/intel/denverton_ns/csme_ie_kt.c
+++ b/src/soc/intel/denverton_ns/csme_ie_kt.c
@@ -38,7 +38,7 @@
struct resource *resource;
resource = pci_get_resource(dev, index);
/**
- * Workarond for Denverton-NS silicon (Rev A0/A1 for CSME/IE,
+ * Workaround for Denverton-NS silicon (Rev A0/A1 for CSME/IE,
* Rev B0 for CSME only)
* CSME&IEs KT IO bar must be 16-byte aligned
*/
@@ -59,7 +59,7 @@
static void pci_csme_ie_kt_read_resources(device_t dev)
{
/**
- * CSME/IE KT has 2 BARs to chec:
+ * CSME/IE KT has 2 BARs to check:
* 0x10 - KT IO BAR
* 0x14 - KT Memory BAR
* CSME/IE KT has no Expansion ROM BAR to check:
diff --git a/src/soc/intel/denverton_ns/gpio.c b/src/soc/intel/denverton_ns/gpio.c
index 3030fbb..1921b13 100644
--- a/src/soc/intel/denverton_ns/gpio.c
+++ b/src/soc/intel/denverton_ns/gpio.c
@@ -284,7 +284,7 @@
(GPIO_CONF_INT_ROUTE_BIT_POS + 1))
<< N_PCH_GPIO_RX_NMI_ROUTE);
- // If CFIO is not Working as GPIO mode, Don't move TxDisabe and
+ // If CFIO is not Working as GPIO mode, Don't move TxDisable and
// RxDisable
if (GpioData->GpioConfig.PadMode == GpioPadModeGpio) {
//
diff --git a/src/soc/intel/denverton_ns/include/soc/bootblock.h b/src/soc/intel/denverton_ns/include/soc/bootblock.h
index 8e58529..5136ecd 100644
--- a/src/soc/intel/denverton_ns/include/soc/bootblock.h
+++ b/src/soc/intel/denverton_ns/include/soc/bootblock.h
@@ -16,13 +16,13 @@
#ifndef _SOC_DENVERTON_NS_BOOTBLOCK_H_
#define _SOC_DENVERTON_NS_BOOTBLOCK_H_
-/* Bootblock pre console init programing */
+/* Bootblock pre console init programming */
//void bootblock_cpu_init(void);
//void bootblock_pch_early_init(void);
//void bootblock_systemagent_early_init(void);
void early_uart_init(void);
-/* Bootblock post console init programing */
+/* Bootblock post console init programming */
//void enable_smbus(void);
//void i2c_early_init(void);
//void pch_early_init(void);
diff --git a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h
index 9b63a08..43e0647 100644
--- a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h
+++ b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h
@@ -141,7 +141,7 @@
#define V_PCH_GPIO_RX_PAD_STATE_RAW 0x00
#define V_PCH_GPIO_RX_PAD_STATE_INT 0x01
-// RX Raw Overrride to 1
+// RX Raw Override to 1
#define B_PCH_GPIO_RX_RAW1 (1 << 28)
#define N_PCH_GPIO_RX_RAW1 28
#define V_PCH_GPIO_RX_RAW1_DIS 0x00
diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h
index fe6dc82..771c3d8 100644
--- a/src/soc/intel/denverton_ns/include/soc/smm.h
+++ b/src/soc/intel/denverton_ns/include/soc/smm.h
@@ -47,7 +47,7 @@
};
/* Fills in the start and size for the requested SMM subregion. Returns
- * 0 on susccess, < 0 on failure. */
+ * 0 on success, < 0 on failure. */
int smm_subregion(int sub, void **start, size_t *size);
#if !defined(__PRE_RAM__) && !defined(__SMM___)
diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c
index 48e81e5..1ac0961 100644
--- a/src/soc/intel/denverton_ns/lpc.c
+++ b/src/soc/intel/denverton_ns/lpc.c
@@ -39,7 +39,7 @@
#define PCH_LP_REDIR_ETR 120
/**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
*
* @param dev PCI device with I/O APIC control registers
*/
diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h
index 62dd234..59ce92a 100644
--- a/src/soc/intel/skylake/include/soc/bootblock.h
+++ b/src/soc/intel/skylake/include/soc/bootblock.h
@@ -24,12 +24,12 @@
static inline void bootblock_fsp_temp_ram_init(void) {}
#endif
-/* Bootblock pre console init programing */
+/* Bootblock pre console init programming */
void bootblock_cpu_init(void);
void bootblock_pch_early_init(void);
void pch_uart_init(void);
-/* Bootblock post console init programing */
+/* Bootblock post console init programming */
void i2c_early_init(void);
void pch_early_init(void);
void pch_early_iorange_init(void);
diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h
index 66b4a01..064ec31 100644
--- a/src/soc/intel/skylake/include/soc/vr_config.h
+++ b/src/soc/intel/skylake/include/soc/vr_config.h
@@ -33,7 +33,7 @@
*/
int vr_config_enable;
- /* Power State X current cuttof in 1/4 Amp increments
+ /* Power State X current cutoff in 1/4 Amp increments
* Range is 0-128A
*/
int psi1threshold;
diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c
index d577896..50119a5 100644
--- a/src/soc/intel/skylake/irq.c
+++ b/src/soc/intel/skylake/irq.c
@@ -233,7 +233,7 @@
sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG));
params->NumOfDevIntConfig = intdeventry;
- /* PxRC to IRQ programing */
+ /* PxRC to IRQ programming */
for (i = 0; i < PCH_MAX_IRQ_CONFIG; i++) {
switch (i) {
case PCH_PARC:
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index c5dc8ac..9151d96 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -122,7 +122,7 @@
/* GDXC MOT */
tracehub_base -= GDXC_MOT_MEMORY_SIZE;
- /* Round down to natual boundary accroding to PSMI size */
+ /* Round down to natural boundary according to PSMI size */
tracehub_base = ALIGN_DOWN(tracehub_base, PSMI_BUFFER_AREA_SIZE);
/* GDXC IOT */
tracehub_base -= GDXC_IOT_MEMORY_SIZE;
diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c
index 8f2fb33..a262462 100644
--- a/src/soc/intel/skylake/romstage/systemagent.c
+++ b/src/soc/intel/skylake/romstage/systemagent.c
@@ -34,12 +34,12 @@
{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
};
- /* Set Fixed MMIO addresss into PCI configuration space */
+ /* Set Fixed MMIO address into PCI configuration space */
sa_set_pci_bar(soc_fixed_pci_resources,
ARRAY_SIZE(soc_fixed_pci_resources));
- /* Set Fixed MMIO addresss into MCH base address */
+ /* Set Fixed MMIO address into MCH base address */
sa_set_mch_bar(soc_fixed_mch_resources,
ARRAY_SIZE(soc_fixed_mch_resources));
- /* Enable PAM regisers */
+ /* Enable PAM registers */
enable_pam_region();
}
diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c
index 8af995d..3227519 100644
--- a/src/soc/intel/skylake/systemagent.c
+++ b/src/soc/intel/skylake/systemagent.c
@@ -28,7 +28,7 @@
/*
* SoC implementation
*
- * Add all known fixed memory ranges for Host Controller/Mmeory
+ * Add all known fixed memory ranges for Host Controller/Memory
* controller.
*/
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
diff --git a/src/soc/marvell/mvmap2315/pmic.c b/src/soc/marvell/mvmap2315/pmic.c
index 89ea5eb..f9fcfc8 100644
--- a/src/soc/marvell/mvmap2315/pmic.c
+++ b/src/soc/marvell/mvmap2315/pmic.c
@@ -92,12 +92,12 @@
void no_boot(void)
{
- /*TODO: impelement no_boot */
+ /*TODO: implement no_boot */
}
void charging_screen(void)
{
- /*TODO: impelement charging_screen */
+ /*TODO: implement charging_screen */
}
void full_boot(void)
diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c
index 7b6444d..8fb839d 100644
--- a/src/soc/nvidia/tegra210/romstage.c
+++ b/src/soc/nvidia/tegra210/romstage.c
@@ -60,7 +60,7 @@
* Trust Zone needs to be initialized after the DRAM initialization
* because carveout registers are programmed during DRAM init.
* cbmem_initialize() is dependent on the Trust Zone region
- * initalization because CBMEM lives right below the Trust Zone which
+ * initialization because CBMEM lives right below the Trust Zone which
* needs to be properly identified.
*/
trustzone_region_init();
diff --git a/src/soc/qualcomm/ipq40xx/blobs_init.c b/src/soc/qualcomm/ipq40xx/blobs_init.c
index 77c0289..2b5e1fd 100644
--- a/src/soc/qualcomm/ipq40xx/blobs_init.c
+++ b/src/soc/qualcomm/ipq40xx/blobs_init.c
@@ -108,7 +108,7 @@
die("Fail to Initialize DDR\n");
/*
- * Once DDR initializer finished, its verison can be found at a fixed
+ * Once DDR initializer finished, its version can be found at a fixed
* address in SRAM.
*/
printk(BIOS_INFO, "DDR version %.*s initialized\n",
diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c
index 5b19fc1..9549e9a 100644
--- a/src/soc/qualcomm/ipq806x/blobs_init.c
+++ b/src/soc/qualcomm/ipq806x/blobs_init.c
@@ -80,7 +80,7 @@
die("Fail to Initialize DDR\n");
/*
- * Once DDR initializer finished, its verison can be found at a fixed
+ * Once DDR initializer finished, its version can be found at a fixed
* address in SRAM.
*/
printk(BIOS_INFO, "DDR version %.*s initialized\n",
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Gerrit-Change-Number: 23706
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
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