<p>Jonathan Neuschäfer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23706">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/soc: Fix various typos<br><br>These typos were found through manual review and grep.<br><br>Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6<br>Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net><br>---<br>M src/soc/amd/stoneyridge/include/soc/northbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>M src/soc/broadcom/cygnus/hw_init.c<br>M src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h<br>M src/soc/imgtec/pistachio/ddr2_init.c<br>M src/soc/imgtec/pistachio/ddr3_init.c<br>M src/soc/intel/apollolake/include/soc/meminit.h<br>M src/soc/intel/apollolake/meminit.c<br>M src/soc/intel/apollolake/romstage.c<br>M src/soc/intel/apollolake/systemagent.c<br>M src/soc/intel/cannonlake/include/soc/bootblock.h<br>M src/soc/intel/cannonlake/include/soc/vr_config.h<br>M src/soc/intel/cannonlake/romstage/systemagent.c<br>M src/soc/intel/cannonlake/systemagent.c<br>M src/soc/intel/common/block/cpu/car/cache_as_ram.S<br>M src/soc/intel/common/block/cse/cse.c<br>M src/soc/intel/common/block/graphics/graphics.c<br>M src/soc/intel/common/block/include/intelblocks/acpi.h<br>M src/soc/intel/common/block/include/intelblocks/lpc_lib.h<br>M src/soc/intel/common/block/include/intelblocks/pmclib.h<br>M src/soc/intel/common/block/include/intelblocks/systemagent.h<br>M src/soc/intel/common/block/pcr/pcr.c<br>M src/soc/intel/common/block/pmc/pmclib.c<br>M src/soc/intel/common/block/sgx/Kconfig<br>M src/soc/intel/common/block/sgx/sgx.c<br>M src/soc/intel/common/block/systemagent/systemagent_def.h<br>M src/soc/intel/common/block/uart/uart.c<br>M src/soc/intel/denverton_ns/bootblock/uart.c<br>M src/soc/intel/denverton_ns/csme_ie_kt.c<br>M src/soc/intel/denverton_ns/gpio.c<br>M src/soc/intel/denverton_ns/include/soc/bootblock.h<br>M src/soc/intel/denverton_ns/include/soc/gpio_defs.h<br>M src/soc/intel/denverton_ns/include/soc/smm.h<br>M src/soc/intel/denverton_ns/lpc.c<br>M src/soc/intel/skylake/include/soc/bootblock.h<br>M src/soc/intel/skylake/include/soc/vr_config.h<br>M src/soc/intel/skylake/irq.c<br>M src/soc/intel/skylake/memmap.c<br>M src/soc/intel/skylake/romstage/systemagent.c<br>M src/soc/intel/skylake/systemagent.c<br>M src/soc/marvell/mvmap2315/pmic.c<br>M src/soc/nvidia/tegra210/romstage.c<br>M src/soc/qualcomm/ipq40xx/blobs_init.c<br>M src/soc/qualcomm/ipq806x/blobs_init.c<br>44 files changed, 82 insertions(+), 82 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/23706/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>index b0bbd54..d649ada 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>@@ -80,7 +80,7 @@</span><br><span> void smm_region_info(void **start, size_t *size);</span><br><span> /*</span><br><span> * Fills in the start and size for the requested SMM subregion. Returns</span><br><span style="color: hsl(0, 100%, 40%);">- * 0 on susccess, < 0 on failure.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 on success, < 0 on failure.</span><br><span> */</span><br><span> int smm_subregion(int sub, void **start, size_t *size);</span><br><span> void domain_enable_resources(device_t dev);</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 735642f..100d4e6 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -75,7 +75,7 @@</span><br><span> </span><br><span> /*</span><br><span> * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME</span><br><span style="color: hsl(0, 100%, 40%);">- * provides a visible association with the index, therefor helping</span><br><span style="color: hsl(120, 100%, 40%);">+ * provides a visible association with the index, therefore helping</span><br><span> * maintainability of table. If a new index/name is defined in</span><br><span> * amd_pci_int_defs.h, just add the pair at the end of this table.</span><br><span> * Order is not important.</span><br><span>diff --git a/src/soc/broadcom/cygnus/hw_init.c b/src/soc/broadcom/cygnus/hw_init.c</span><br><span>index b9e5857..ce5592f 100644</span><br><span>--- a/src/soc/broadcom/cygnus/hw_init.c</span><br><span>+++ b/src/soc/broadcom/cygnus/hw_init.c</span><br><span>@@ -106,7 +106,7 @@</span><br><span> *</span><br><span> * NOTE: In the future, we might want to protect particular CRMU</span><br><span> * sub-blocks to allow SECURE access only. That can be done by</span><br><span style="color: hsl(0, 100%, 40%);">- * programing the CRMU IPROC address range registers. Up to 4 access</span><br><span style="color: hsl(120, 100%, 40%);">+ * programming the CRMU IPROC address range registers. Up to 4 access</span><br><span> * windows can be created</span><br><span> */</span><br><span> write32((void *)CRMU_IPROC_ADDR_RANGE0_LOW,</span><br><span>diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h</span><br><span>index 166cc0b..93489bb 100644</span><br><span>--- a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h</span><br><span>+++ b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h</span><br><span>@@ -218,7 +218,7 @@</span><br><span> #define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC 0x000004a0 /* Read enable bit-clock cycle delay control register */</span><br><span> #define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC 0x000004a4 /* Write leveling bit-clock cycle delay control register */</span><br><span> #define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL 0x000004b0 /* Read channel datapath control register */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR 0x000004b4 /* Read fifo addresss pointer register */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR 0x000004b4 /* Read fifo address pointer register */</span><br><span> #define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DATA 0x000004b8 /* Read fifo data register */</span><br><span> #define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI 0x000004bc /* Read fifo dm/dbi register */</span><br><span> #define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS 0x000004c0 /* Read fifo status register */</span><br><span>@@ -284,7 +284,7 @@</span><br><span> #define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC 0x000006a0 /* Read enable bit-clock cycle delay control register */</span><br><span> #define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC 0x000006a4 /* Write leveling bit-clock cycle delay control register */</span><br><span> #define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL 0x000006b0 /* Read channel datapath control register */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR 0x000006b4 /* Read fifo addresss pointer register */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR 0x000006b4 /* Read fifo address pointer register */</span><br><span> #define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DATA 0x000006b8 /* Read fifo data register */</span><br><span> #define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI 0x000006bc /* Read fifo dm/dbi register */</span><br><span> #define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS 0x000006c0 /* Read fifo status register */</span><br><span>@@ -7729,7 +7729,7 @@</span><br><span> #define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007</span><br><span> </span><br><span> /***************************************************************************</span><br><span style="color: hsl(0, 100%, 40%);">- *READ_FIFO_ADDR - Read fifo addresss pointer register</span><br><span style="color: hsl(120, 100%, 40%);">+ *READ_FIFO_ADDR - Read fifo address pointer register</span><br><span> ***************************************************************************/</span><br><span> /* DDR34_CORE_PHY_BYTE_LANE_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */</span><br><span> #define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8</span><br><span>@@ -10483,7 +10483,7 @@</span><br><span> #define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007</span><br><span> </span><br><span> /***************************************************************************</span><br><span style="color: hsl(0, 100%, 40%);">- *READ_FIFO_ADDR - Read fifo addresss pointer register</span><br><span style="color: hsl(120, 100%, 40%);">+ *READ_FIFO_ADDR - Read fifo address pointer register</span><br><span> ***************************************************************************/</span><br><span> /* DDR34_CORE_PHY_BYTE_LANE_1 :: READ_FIFO_ADDR :: reserved0 [31:03] */</span><br><span> #define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8</span><br><span>diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c</span><br><span>index 9549537..aac85a9 100644</span><br><span>--- a/src/soc/imgtec/pistachio/ddr2_init.c</span><br><span>+++ b/src/soc/imgtec/pistachio/ddr2_init.c</span><br><span>@@ -288,7 +288,7 @@</span><br><span> */</span><br><span> write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x00000012);</span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * TRC : Min. ROW cylce time</span><br><span style="color: hsl(120, 100%, 40%);">+ * TRC : Min. ROW cycle time</span><br><span> * Range 11 to 31: 57.5ns / 2.5ns = 23d Playing safe 24</span><br><span> */</span><br><span> write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000018);</span><br><span>diff --git a/src/soc/imgtec/pistachio/ddr3_init.c b/src/soc/imgtec/pistachio/ddr3_init.c</span><br><span>index 5cb36a0..b3f723c 100644</span><br><span>--- a/src/soc/imgtec/pistachio/ddr3_init.c</span><br><span>+++ b/src/soc/imgtec/pistachio/ddr3_init.c</span><br><span>@@ -303,7 +303,7 @@</span><br><span> write32(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005);</span><br><span> /* TRAS : Activate to Precharge cmd time 15 45ns / 2.5ns = 18d */</span><br><span> write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x0000000F);</span><br><span style="color: hsl(0, 100%, 40%);">- /* TRC : Min. ROW cylce time 21</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TRC : Min. ROW cycle time 21</span><br><span> * 57.5ns / 2.5ns = 23d Playing safe 24</span><br><span> */</span><br><span> write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000015);</span><br><span>@@ -428,7 +428,7 @@</span><br><span> */</span><br><span> write32(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x060600000);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Memory initilization */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Memory initialization */</span><br><span> /* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0</span><br><span> * 3:0 cmd_opcode PREA 00001</span><br><span> * 16:4 cmd_addr 0</span><br><span>diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h</span><br><span>index 339d2b1..fa12728 100644</span><br><span>--- a/src/soc/intel/apollolake/include/soc/meminit.h</span><br><span>+++ b/src/soc/intel/apollolake/include/soc/meminit.h</span><br><span>@@ -76,7 +76,7 @@</span><br><span> * and LOW for ODT_B, choose ODT_AB_HIGH_LOW.</span><br><span> *</span><br><span> * Note that the enum values correspond to the interpreted UPD fields</span><br><span style="color: hsl(0, 100%, 40%);">- * witihn Ch[3:0]_OdtConfig parameters.</span><br><span style="color: hsl(120, 100%, 40%);">+ * within Ch[3:0]_OdtConfig parameters.</span><br><span> */</span><br><span> enum {</span><br><span> ODT_A_B_HIGH_LOW = 0 << 1,</span><br><span>diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c</span><br><span>index 91cdeb5..dd8b591 100644</span><br><span>--- a/src/soc/intel/apollolake/meminit.c</span><br><span>+++ b/src/soc/intel/apollolake/meminit.c</span><br><span>@@ -130,10 +130,10 @@</span><br><span> /*</span><br><span> * CH0_DQB byte lanes in the bit swizzle configuration field are</span><br><span> * not 1:1. The mapping within the swizzling field is:</span><br><span style="color: hsl(0, 100%, 40%);">- * indicies [0:7] - byte lane 1 (DQS1) DQ[8:15]</span><br><span style="color: hsl(0, 100%, 40%);">- * indicies [8:15] - byte lane 0 (DQS0) DQ[0:7]</span><br><span style="color: hsl(0, 100%, 40%);">- * indicies [16:23] - byte lane 3 (DQS3) DQ[24:31]</span><br><span style="color: hsl(0, 100%, 40%);">- * indicies [24:31] - byte lane 2 (DQS2) DQ[16:23]</span><br><span style="color: hsl(120, 100%, 40%);">+ * indices [0:7] - byte lane 1 (DQS1) DQ[8:15]</span><br><span style="color: hsl(120, 100%, 40%);">+ * indices [8:15] - byte lane 0 (DQS0) DQ[0:7]</span><br><span style="color: hsl(120, 100%, 40%);">+ * indices [16:23] - byte lane 3 (DQS3) DQ[24:31]</span><br><span style="color: hsl(120, 100%, 40%);">+ * indices [24:31] - byte lane 2 (DQS2) DQ[16:23]</span><br><span> */</span><br><span> chan = &scfg->phys[LP4_PHYS_CH0B];</span><br><span> memcpy(&cfg->Ch0_Bit_swizzling[0], &chan->dqs[LP4_DQS1], sz);</span><br><span>@@ -175,10 +175,10 @@</span><br><span> /*</span><br><span> * CH1_DQB byte lanes in the bit swizzle configuration field are</span><br><span> * not 1:1. The mapping within the swizzling field is:</span><br><span style="color: hsl(0, 100%, 40%);">- * indicies [0:7] - byte lane 1 (DQS1) DQ[8:15]</span><br><span style="color: hsl(0, 100%, 40%);">- * indicies [8:15] - byte lane 0 (DQS0) DQ[0:7]</span><br><span style="color: hsl(0, 100%, 40%);">- * indicies [16:23] - byte lane 3 (DQS3) DQ[24:31]</span><br><span style="color: hsl(0, 100%, 40%);">- * indicies [24:31] - byte lane 2 (DQS2) DQ[16:23]</span><br><span style="color: hsl(120, 100%, 40%);">+ * indices [0:7] - byte lane 1 (DQS1) DQ[8:15]</span><br><span style="color: hsl(120, 100%, 40%);">+ * indices [8:15] - byte lane 0 (DQS0) DQ[0:7]</span><br><span style="color: hsl(120, 100%, 40%);">+ * indices [16:23] - byte lane 3 (DQS3) DQ[24:31]</span><br><span style="color: hsl(120, 100%, 40%);">+ * indices [24:31] - byte lane 2 (DQS2) DQ[16:23]</span><br><span> */</span><br><span> chan = &scfg->phys[LP4_PHYS_CH1B];</span><br><span> memcpy(&cfg->Ch2_Bit_swizzling[0], &chan->dqs[LP4_DQS1], sz);</span><br><span>diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c</span><br><span>index 20b67fd..1db2982 100644</span><br><span>--- a/src/soc/intel/apollolake/romstage.c</span><br><span>+++ b/src/soc/intel/apollolake/romstage.c</span><br><span>@@ -87,7 +87,7 @@</span><br><span> { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Fixed MMIO addresss into PCI configuration space */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Fixed MMIO address into PCI configuration space */</span><br><span> sa_set_pci_bar(soc_fixed_pci_resources,</span><br><span> ARRAY_SIZE(soc_fixed_pci_resources));</span><br><span> </span><br><span>diff --git a/src/soc/intel/apollolake/systemagent.c b/src/soc/intel/apollolake/systemagent.c</span><br><span>index 57de4b8..c8f1330 100644</span><br><span>--- a/src/soc/intel/apollolake/systemagent.c</span><br><span>+++ b/src/soc/intel/apollolake/systemagent.c</span><br><span>@@ -27,7 +27,7 @@</span><br><span> /*</span><br><span> * SoC implementation</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Add all known fixed memory ranges for Host Controller/Mmeory</span><br><span style="color: hsl(120, 100%, 40%);">+ * Add all known fixed memory ranges for Host Controller/Memory</span><br><span> * controller.</span><br><span> */</span><br><span> void soc_add_fixed_mmio_resources(struct device *dev, int *index)</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/bootblock.h b/src/soc/intel/cannonlake/include/soc/bootblock.h</span><br><span>index 2a6ca1f..a5c3c32 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/bootblock.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/bootblock.h</span><br><span>@@ -18,11 +18,11 @@</span><br><span> </span><br><span> #include <intelblocks/systemagent.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Bootblock pre console init programing */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Bootblock pre console init programming */</span><br><span> void bootblock_cpu_init(void);</span><br><span> void bootblock_pch_early_init(void);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Bootblock post console init programing */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Bootblock post console init programming */</span><br><span> void pch_early_init(void);</span><br><span> void pch_early_iorange_init(void);</span><br><span> void report_platform_info(void);</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h</span><br><span>index 2cd7dd9..385767d 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/vr_config.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/vr_config.h</span><br><span>@@ -26,7 +26,7 @@</span><br><span> * for that domain. */</span><br><span> uint8_t vr_config_enable;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Power State X current cuttof in 1/4 Amp increments</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Power State X current cutoff in 1/4 Amp increments</span><br><span> * Range is 0-128A */</span><br><span> uint16_t psi1threshold;</span><br><span> uint16_t psi2threshold;</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/systemagent.c b/src/soc/intel/cannonlake/romstage/systemagent.c</span><br><span>index f7c7f1a..61db22e 100644</span><br><span>--- a/src/soc/intel/cannonlake/romstage/systemagent.c</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/systemagent.c</span><br><span>@@ -34,12 +34,12 @@</span><br><span> { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Fixed MMIO addresss into PCI configuration space */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Fixed MMIO address into PCI configuration space */</span><br><span> sa_set_pci_bar(soc_fixed_pci_resources,</span><br><span> ARRAY_SIZE(soc_fixed_pci_resources));</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Fixed MMIO addresss into MCH base address */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Fixed MMIO address into MCH base address */</span><br><span> sa_set_mch_bar(soc_fixed_mch_resources,</span><br><span> ARRAY_SIZE(soc_fixed_mch_resources));</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable PAM regisers */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable PAM registers */</span><br><span> enable_pam_region();</span><br><span> }</span><br><span>diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c</span><br><span>index 344517d..06b37e0 100644</span><br><span>--- a/src/soc/intel/cannonlake/systemagent.c</span><br><span>+++ b/src/soc/intel/cannonlake/systemagent.c</span><br><span>@@ -25,7 +25,7 @@</span><br><span> /*</span><br><span> * SoC implementation</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Add all known fixed memory ranges for Host Controller/Mmeory</span><br><span style="color: hsl(120, 100%, 40%);">+ * Add all known fixed memory ranges for Host Controller/Memory</span><br><span> * controller.</span><br><span> */</span><br><span> void soc_add_fixed_mmio_resources(struct device *dev, int *index)</span><br><span>diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S</span><br><span>index 1798de5..02aeefe 100644</span><br><span>--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S</span><br><span>+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S</span><br><span>@@ -389,7 +389,7 @@</span><br><span> * Maximizing RO cacheability while locking in the CAR to a</span><br><span> * single way since that particular way won't be victim candidate</span><br><span> * for evictions.</span><br><span style="color: hsl(0, 100%, 40%);">- * This has been done after programing LLC_WAY_MASK_1 MSR</span><br><span style="color: hsl(120, 100%, 40%);">+ * This has been done after programming LLC_WAY_MASK_1 MSR</span><br><span> * with desired LLC way as mentioned below.</span><br><span> *</span><br><span> * Hence create Code and Data Size as per request</span><br><span>diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c</span><br><span>index 0ff999e..4991db6 100644</span><br><span>--- a/src/soc/intel/common/block/cse/cse.c</span><br><span>+++ b/src/soc/intel/common/block/cse/cse.c</span><br><span>@@ -31,7 +31,7 @@</span><br><span> </span><br><span> /* Wait up to 15 sec for HECI to get ready */</span><br><span> #define HECI_DELAY_READY (15 * 1000)</span><br><span style="color: hsl(0, 100%, 40%);">-/* Wait up to 100 usec between circullar buffer polls */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Wait up to 100 usec between circular buffer polls */</span><br><span> #define HECI_DELAY 100</span><br><span> /* Wait up to 5 sec for CSE to chew something we sent */</span><br><span> #define HECI_SEND_TIMEOUT (5 * 1000)</span><br><span>@@ -126,7 +126,7 @@</span><br><span> static uint32_t read_bar(uint32_t offset)</span><br><span> {</span><br><span> struct cse_device *cse = car_get_var_ptr(&g_cse);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Reach PCI config space to get BAR incase CAR global not available */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Reach PCI config space to get BAR in case CAR global not available */</span><br><span> if (!cse->sec_bar)</span><br><span> cse->sec_bar = get_cse_bar();</span><br><span> return read32((void *)(cse->sec_bar + offset));</span><br><span>@@ -135,7 +135,7 @@</span><br><span> static void write_bar(uint32_t offset, uint32_t val)</span><br><span> {</span><br><span> struct cse_device *cse = car_get_var_ptr(&g_cse);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Reach PCI config space to get BAR incase CAR global not available */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Reach PCI config space to get BAR in case CAR global not available */</span><br><span> if (!cse->sec_bar)</span><br><span> cse->sec_bar = get_cse_bar();</span><br><span> return write32((void *)(cse->sec_bar + offset), val);</span><br><span>@@ -341,7 +341,7 @@</span><br><span> </span><br><span> /*</span><br><span> * Fragment the message into smaller messages not exceeding</span><br><span style="color: hsl(0, 100%, 40%);">- * useful circullar buffer length. Mark last message complete.</span><br><span style="color: hsl(120, 100%, 40%);">+ * useful circular buffer length. Mark last message complete.</span><br><span> */</span><br><span> do {</span><br><span> hdr = MIN(max_length, remaining)</span><br><span>diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c</span><br><span>index 5b2527c..dcf8200 100644</span><br><span>--- a/src/soc/intel/common/block/graphics/graphics.c</span><br><span>+++ b/src/soc/intel/common/block/graphics/graphics.c</span><br><span>@@ -24,7 +24,7 @@</span><br><span> __attribute__((weak)) void graphics_soc_init(struct device *dev)</span><br><span> {</span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * User needs to implement SoC override incase wishes</span><br><span style="color: hsl(120, 100%, 40%);">+ * User needs to implement SoC override in case wishes</span><br><span> * to perform certain specific graphics initialization</span><br><span> * along with pci_dev_init(dev)</span><br><span> */</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h</span><br><span>index 73a9c9c..927da3c 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/acpi.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/acpi.h</span><br><span>@@ -44,7 +44,7 @@</span><br><span> struct acpi_rsdp *rsdp);</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Craetes acpi gnvs and adds it to the DSDT table.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Creates acpi gnvs and adds it to the DSDT table.</span><br><span> * GNVS creation is chipset specific and is done in soc specific acpi.c file.</span><br><span> */</span><br><span> void southbridge_inject_dsdt(device_t device);</span><br><span>@@ -84,7 +84,7 @@</span><br><span> /*</span><br><span> * soc specific power states generation. We need this to be defined by soc</span><br><span> * as the state generations varies in chipsets e.g. APL generates T and P</span><br><span style="color: hsl(0, 100%, 40%);">- * states while SKL generates * P state only depening on a devicetree config</span><br><span style="color: hsl(120, 100%, 40%);">+ * states while SKL generates * P state only depending on a devicetree config</span><br><span> */</span><br><span> void soc_power_states_generation(int core_id, int cores_per_package);</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h</span><br><span>index 554c75d..7269bef 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h</span><br><span>@@ -69,14 +69,14 @@</span><br><span> void lpc_open_mmio_window(uintptr_t base, size_t size);</span><br><span> /* Returns true if given window is decoded to LPC via a fixed range. */</span><br><span> bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size);</span><br><span style="color: hsl(0, 100%, 40%);">-/* Init SoC Spcific LPC features. Common definition will be weak and</span><br><span style="color: hsl(120, 100%, 40%);">+/* Init SoC Specific LPC features. Common definition will be weak and</span><br><span> each soc will need to define the init. */</span><br><span> void lpc_soc_init(struct device *dev);</span><br><span> /* Fill up LPC IO resource structure inside SoC directory */</span><br><span> void pch_lpc_soc_fill_io_resources(struct device *dev);</span><br><span> /* Init LPC GPIO pads */</span><br><span> void lpc_configure_pads(void);</span><br><span style="color: hsl(0, 100%, 40%);">-/* Get SoC speicific MMIO ranges */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Get SoC specific MMIO ranges */</span><br><span> const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void);</span><br><span> /* Set LPC BIOS Control BILD bit. */</span><br><span> void lpc_set_bios_interface_lock_down(void);</span><br><span>@@ -97,7 +97,7 @@</span><br><span> void lpc_io_setup_comm_a_b(void);</span><br><span> /* Enable PCH LPC by setting up generic decode range registers. */</span><br><span> void pch_enable_lpc(void);</span><br><span style="color: hsl(0, 100%, 40%);">-/* Retrieve and setup SoC speicific PCH LPC interrupt routing. */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Retrieve and setup SoC specific PCH LPC interrupt routing. */</span><br><span> void soc_pch_pirq_init(const struct device *dev);</span><br><span> /* Get SoC's generic IO decoder range register settings. */</span><br><span> void soc_get_gen_io_dec_range(const struct device *dev,</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h</span><br><span>index 3827cf5..d631f01 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/pmclib.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h</span><br><span>@@ -37,7 +37,7 @@</span><br><span> /*</span><br><span> * This function is specific to soc and is defined as weak in common</span><br><span> * pmclib file. SOC code can implement it for any special condition</span><br><span style="color: hsl(0, 100%, 40%);">- * specific to the soc e.g. in SKL in handles deep S3 scenerio.</span><br><span style="color: hsl(120, 100%, 40%);">+ * specific to the soc e.g. in SKL in handles deep S3 scenario.</span><br><span> * Return ACPI_SX values to indicate the previous sleep state.</span><br><span> */</span><br><span> int soc_prev_sleep_state(const struct chipset_power_state *ps,</span><br><span>@@ -206,7 +206,7 @@</span><br><span> void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2);</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Reads soc specific power management crtitical registers, fills</span><br><span style="color: hsl(120, 100%, 40%);">+ * Reads soc specific power management critical registers, fills</span><br><span> * chipset_power_state structure variable and prints.</span><br><span> */</span><br><span> void soc_fill_power_state(struct chipset_power_state *ps);</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h</span><br><span>index 64b2c36..a731b9c 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/systemagent.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h</span><br><span>@@ -52,10 +52,10 @@</span><br><span> const char *description;</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* API to set Fixed MMIO addresss into PCI configuration space */</span><br><span style="color: hsl(120, 100%, 40%);">+/* API to set Fixed MMIO address into PCI configuration space */</span><br><span> void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources,</span><br><span> size_t count);</span><br><span style="color: hsl(0, 100%, 40%);">-/* API to set Fixed MMIO addresss into MCH base address */</span><br><span style="color: hsl(120, 100%, 40%);">+/* API to set Fixed MMIO address into MCH base address */</span><br><span> void sa_set_mch_bar(const struct sa_mmio_descriptor *fixed_set_resources,</span><br><span> size_t count);</span><br><span> /*</span><br><span>@@ -69,7 +69,7 @@</span><br><span> * SoC to provide BIOS_RESET_CPL register offset through soc/systemagent.h</span><br><span> */</span><br><span> void enable_bios_reset_cpl(void);</span><br><span style="color: hsl(0, 100%, 40%);">-/* API to enable PAM regisers */</span><br><span style="color: hsl(120, 100%, 40%);">+/* API to enable PAM registers */</span><br><span> void enable_pam_region(void);</span><br><span> /* API to enable Power Aware Interrupt Routing through MCHBAR */</span><br><span> void enable_power_aware_intr(void);</span><br><span>diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c</span><br><span>index 4264cdf..e106c41 100644</span><br><span>--- a/src/soc/intel/common/block/pcr/pcr.c</span><br><span>+++ b/src/soc/intel/common/block/pcr/pcr.c</span><br><span>@@ -59,7 +59,7 @@</span><br><span> </span><br><span> uint32_t pcr_read32(uint8_t pid, uint16_t offset)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Ensure the PCR offset is corretcly aligned. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Ensure the PCR offset is correctly aligned. */</span><br><span> assert(IS_ALIGNED(offset, sizeof(uint32_t)));</span><br><span> </span><br><span> return read32(__pcr_reg_address(pid, offset));</span><br><span>@@ -67,7 +67,7 @@</span><br><span> </span><br><span> uint16_t pcr_read16(uint8_t pid, uint16_t offset)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Ensure the PCR offset is corretcly aligned. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Ensure the PCR offset is correctly aligned. */</span><br><span> check_pcr_offset_align(offset, sizeof(uint16_t));</span><br><span> </span><br><span> return read16(__pcr_reg_address(pid, offset));</span><br><span>@@ -75,7 +75,7 @@</span><br><span> </span><br><span> uint8_t pcr_read8(uint8_t pid, uint16_t offset)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Ensure the PCR offset is corretcly aligned. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Ensure the PCR offset is correctly aligned. */</span><br><span> check_pcr_offset_align(offset, sizeof(uint8_t));</span><br><span> </span><br><span> return read8(__pcr_reg_address(pid, offset));</span><br><span>@@ -94,7 +94,7 @@</span><br><span> </span><br><span> void pcr_write32(uint8_t pid, uint16_t offset, uint32_t indata)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Ensure the PCR offset is corretcly aligned. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Ensure the PCR offset is correctly aligned. */</span><br><span> assert(IS_ALIGNED(offset, sizeof(indata)));</span><br><span> </span><br><span> write32(__pcr_reg_address(pid, offset), indata);</span><br><span>@@ -104,7 +104,7 @@</span><br><span> </span><br><span> void pcr_write16(uint8_t pid, uint16_t offset, uint16_t indata)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Ensure the PCR offset is corretcly aligned. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Ensure the PCR offset is correctly aligned. */</span><br><span> check_pcr_offset_align(offset, sizeof(uint16_t));</span><br><span> </span><br><span> write16(__pcr_reg_address(pid, offset), indata);</span><br><span>@@ -114,7 +114,7 @@</span><br><span> </span><br><span> void pcr_write8(uint8_t pid, uint16_t offset, uint8_t indata)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Ensure the PCR offset is corretcly aligned. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Ensure the PCR offset is correctly aligned. */</span><br><span> check_pcr_offset_align(offset, sizeof(uint8_t));</span><br><span> </span><br><span> write8(__pcr_reg_address(pid, offset), indata);</span><br><span>diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c</span><br><span>index dea7e1b..cf87d05 100644</span><br><span>--- a/src/soc/intel/common/block/pmc/pmclib.c</span><br><span>+++ b/src/soc/intel/common/block/pmc/pmclib.c</span><br><span>@@ -360,7 +360,7 @@</span><br><span> </span><br><span> /*</span><br><span> * Returns prev_sleep_state and also prints all power management registers.</span><br><span style="color: hsl(0, 100%, 40%);">- * Calls soc_prev_sleep_state which may be impelmented by SOC.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Calls soc_prev_sleep_state which may be implemented by SOC.</span><br><span> */</span><br><span> static int pmc_prev_sleep_state(const struct chipset_power_state *ps)</span><br><span> {</span><br><span>diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig</span><br><span>index 7889582..0852bfb 100644</span><br><span>--- a/src/soc/intel/common/block/sgx/Kconfig</span><br><span>+++ b/src/soc/intel/common/block/sgx/Kconfig</span><br><span>@@ -3,5 +3,5 @@</span><br><span> default n</span><br><span> help</span><br><span> Software Guard eXtension(SGX) Feature. Intel SGX is a set of new CPU</span><br><span style="color: hsl(0, 100%, 40%);">- instructions that can be used by applications to set aside privat</span><br><span style="color: hsl(120, 100%, 40%);">+ instructions that can be used by applications to set aside private</span><br><span> regions of code and data.</span><br><span>diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c</span><br><span>index 86789fa..d3be15c 100644</span><br><span>--- a/src/soc/intel/common/block/sgx/sgx.c</span><br><span>+++ b/src/soc/intel/common/block/sgx/sgx.c</span><br><span>@@ -193,11 +193,11 @@</span><br><span> msr_t msr;</span><br><span> msr = rdmsr(PRMRR_PHYS_MASK_MSR);</span><br><span> if (msr.lo & PRMRR_PHYS_MASK_VALID) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "SGX: MCHECK aprroved SGX PRMRR\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "SGX: MCHECK approved SGX PRMRR\n");</span><br><span> return 1;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "SGX: MCHECK did not aprrove SGX PRMRR\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "SGX: MCHECK did not approve SGX PRMRR\n");</span><br><span> return 0;</span><br><span> }</span><br><span> </span><br><span>@@ -226,7 +226,7 @@</span><br><span> /* Lock the SGX feature */</span><br><span> lock_sgx();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Activate the SGX feature, if PRMRR config was aprroved by MCHECK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Activate the SGX feature, if PRMRR config was approved by MCHECK */</span><br><span> if (is_prmrr_approved())</span><br><span> activate_sgx();</span><br><span> }</span><br><span>diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h</span><br><span>index e028692..b89a10d 100644</span><br><span>--- a/src/soc/intel/common/block/systemagent/systemagent_def.h</span><br><span>+++ b/src/soc/intel/common/block/systemagent/systemagent_def.h</span><br><span>@@ -19,13 +19,13 @@</span><br><span> </span><br><span> /* Device 0:0.0 PCI configuration space */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* GMCH Graphics Comntrol Register */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GMCH Graphics Control Register */</span><br><span> #define GGC 0x50</span><br><span> #define G_GMS_OFFSET 0x8</span><br><span> #define G_GMS_MASK 0xff00</span><br><span> #define G_GGMS_OFFSET 0x6</span><br><span> #define G_GGMS_MASK 0xc0</span><br><span style="color: hsl(0, 100%, 40%);">-/* DPR register incase CONFIG_SA_ENABLE_DPR is selected by SoC */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DPR register in case CONFIG_SA_ENABLE_DPR is selected by SoC */</span><br><span> #define DPR 0x5c</span><br><span> #define DPR_EPM (1 << 2)</span><br><span> #define DPR_PRS (1 << 1)</span><br><span>@@ -48,7 +48,7 @@</span><br><span> #define MCH_PAIR 0x5418</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * IMR register incase CONFIG_SA_ENABLE_IMR is selected by SoC.</span><br><span style="color: hsl(120, 100%, 40%);">+ * IMR register in case CONFIG_SA_ENABLE_IMR is selected by SoC.</span><br><span> *</span><br><span> * IMR registers are found under MCHBAR.</span><br><span> */</span><br><span>diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c</span><br><span>index 91badc7..9f26ef1 100644</span><br><span>--- a/src/soc/intel/common/block/uart/uart.c</span><br><span>+++ b/src/soc/intel/common/block/uart/uart.c</span><br><span>@@ -106,7 +106,7 @@</span><br><span> static bool uart_controller_needs_init(struct device *dev)</span><br><span> {</span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * If coreboot has CONSOLE_SERIAL enabled, the skip re-initalizing</span><br><span style="color: hsl(120, 100%, 40%);">+ * If coreboot has CONSOLE_SERIAL enabled, the skip re-initializing</span><br><span> * controller here.</span><br><span> */</span><br><span> if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))</span><br><span>diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c</span><br><span>index a81b389..affddba 100644</span><br><span>--- a/src/soc/intel/denverton_ns/bootblock/uart.c</span><br><span>+++ b/src/soc/intel/denverton_ns/bootblock/uart.c</span><br><span>@@ -185,7 +185,7 @@</span><br><span> {</span><br><span> register int i;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Check: do we have enought elements to init. ? */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Check: do we have enough elements to init. ? */</span><br><span> BUILD_BUG_ON(DENVERTON_UARTS_TO_INI > ELEM_OF_UART_TAB);</span><br><span> </span><br><span> /* HSUART(B0:D26:0-1) GPIO init. */</span><br><span>diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c</span><br><span>index 7848883..7de0976 100644</span><br><span>--- a/src/soc/intel/denverton_ns/csme_ie_kt.c</span><br><span>+++ b/src/soc/intel/denverton_ns/csme_ie_kt.c</span><br><span>@@ -38,7 +38,7 @@</span><br><span> struct resource *resource;</span><br><span> resource = pci_get_resource(dev, index);</span><br><span> /**</span><br><span style="color: hsl(0, 100%, 40%);">- * Workarond for Denverton-NS silicon (Rev A0/A1 for CSME/IE,</span><br><span style="color: hsl(120, 100%, 40%);">+ * Workaround for Denverton-NS silicon (Rev A0/A1 for CSME/IE,</span><br><span> * Rev B0 for CSME only)</span><br><span> * CSME&IEs KT IO bar must be 16-byte aligned</span><br><span> */</span><br><span>@@ -59,7 +59,7 @@</span><br><span> static void pci_csme_ie_kt_read_resources(device_t dev)</span><br><span> {</span><br><span> /**</span><br><span style="color: hsl(0, 100%, 40%);">- * CSME/IE KT has 2 BARs to chec:</span><br><span style="color: hsl(120, 100%, 40%);">+ * CSME/IE KT has 2 BARs to check:</span><br><span> * 0x10 - KT IO BAR</span><br><span> * 0x14 - KT Memory BAR</span><br><span> * CSME/IE KT has no Expansion ROM BAR to check:</span><br><span>diff --git a/src/soc/intel/denverton_ns/gpio.c b/src/soc/intel/denverton_ns/gpio.c</span><br><span>index 3030fbb..1921b13 100644</span><br><span>--- a/src/soc/intel/denverton_ns/gpio.c</span><br><span>+++ b/src/soc/intel/denverton_ns/gpio.c</span><br><span>@@ -284,7 +284,7 @@</span><br><span> (GPIO_CONF_INT_ROUTE_BIT_POS + 1))</span><br><span> << N_PCH_GPIO_RX_NMI_ROUTE);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- // If CFIO is not Working as GPIO mode, Don't move TxDisabe and</span><br><span style="color: hsl(120, 100%, 40%);">+ // If CFIO is not Working as GPIO mode, Don't move TxDisable and</span><br><span> // RxDisable</span><br><span> if (GpioData->GpioConfig.PadMode == GpioPadModeGpio) {</span><br><span> //</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/bootblock.h b/src/soc/intel/denverton_ns/include/soc/bootblock.h</span><br><span>index 8e58529..5136ecd 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/bootblock.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/bootblock.h</span><br><span>@@ -16,13 +16,13 @@</span><br><span> #ifndef _SOC_DENVERTON_NS_BOOTBLOCK_H_</span><br><span> #define _SOC_DENVERTON_NS_BOOTBLOCK_H_</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Bootblock pre console init programing */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Bootblock pre console init programming */</span><br><span> //void bootblock_cpu_init(void);</span><br><span> //void bootblock_pch_early_init(void);</span><br><span> //void bootblock_systemagent_early_init(void);</span><br><span> void early_uart_init(void);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Bootblock post console init programing */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Bootblock post console init programming */</span><br><span> //void enable_smbus(void);</span><br><span> //void i2c_early_init(void);</span><br><span> //void pch_early_init(void);</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h</span><br><span>index 9b63a08..43e0647 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h</span><br><span>@@ -141,7 +141,7 @@</span><br><span> #define V_PCH_GPIO_RX_PAD_STATE_RAW 0x00</span><br><span> #define V_PCH_GPIO_RX_PAD_STATE_INT 0x01</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-// RX Raw Overrride to 1</span><br><span style="color: hsl(120, 100%, 40%);">+// RX Raw Override to 1</span><br><span> #define B_PCH_GPIO_RX_RAW1 (1 << 28)</span><br><span> #define N_PCH_GPIO_RX_RAW1 28</span><br><span> #define V_PCH_GPIO_RX_RAW1_DIS 0x00</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h</span><br><span>index fe6dc82..771c3d8 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/smm.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/smm.h</span><br><span>@@ -47,7 +47,7 @@</span><br><span> };</span><br><span> </span><br><span> /* Fills in the start and size for the requested SMM subregion. Returns</span><br><span style="color: hsl(0, 100%, 40%);">- * 0 on susccess, < 0 on failure. */</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 on success, < 0 on failure. */</span><br><span> int smm_subregion(int sub, void **start, size_t *size);</span><br><span> </span><br><span> #if !defined(__PRE_RAM__) && !defined(__SMM___)</span><br><span>diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c</span><br><span>index 48e81e5..1ac0961 100644</span><br><span>--- a/src/soc/intel/denverton_ns/lpc.c</span><br><span>+++ b/src/soc/intel/denverton_ns/lpc.c</span><br><span>@@ -39,7 +39,7 @@</span><br><span> #define PCH_LP_REDIR_ETR 120</span><br><span> </span><br><span> /**</span><br><span style="color: hsl(0, 100%, 40%);">- * Set miscellanous static southbridge features.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set miscellaneous static southbridge features.</span><br><span> *</span><br><span> * @param dev PCI device with I/O APIC control registers</span><br><span> */</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h</span><br><span>index 62dd234..59ce92a 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/bootblock.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/bootblock.h</span><br><span>@@ -24,12 +24,12 @@</span><br><span> static inline void bootblock_fsp_temp_ram_init(void) {}</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Bootblock pre console init programing */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Bootblock pre console init programming */</span><br><span> void bootblock_cpu_init(void);</span><br><span> void bootblock_pch_early_init(void);</span><br><span> void pch_uart_init(void);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Bootblock post console init programing */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Bootblock post console init programming */</span><br><span> void i2c_early_init(void);</span><br><span> void pch_early_init(void);</span><br><span> void pch_early_iorange_init(void);</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h</span><br><span>index 66b4a01..064ec31 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/vr_config.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/vr_config.h</span><br><span>@@ -33,7 +33,7 @@</span><br><span> */</span><br><span> int vr_config_enable;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Power State X current cuttof in 1/4 Amp increments</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Power State X current cutoff in 1/4 Amp increments</span><br><span> * Range is 0-128A</span><br><span> */</span><br><span> int psi1threshold;</span><br><span>diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c</span><br><span>index d577896..50119a5 100644</span><br><span>--- a/src/soc/intel/skylake/irq.c</span><br><span>+++ b/src/soc/intel/skylake/irq.c</span><br><span>@@ -233,7 +233,7 @@</span><br><span> sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG));</span><br><span> </span><br><span> params->NumOfDevIntConfig = intdeventry;</span><br><span style="color: hsl(0, 100%, 40%);">- /* PxRC to IRQ programing */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PxRC to IRQ programming */</span><br><span> for (i = 0; i < PCH_MAX_IRQ_CONFIG; i++) {</span><br><span> switch (i) {</span><br><span> case PCH_PARC:</span><br><span>diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c</span><br><span>index c5dc8ac..9151d96 100644</span><br><span>--- a/src/soc/intel/skylake/memmap.c</span><br><span>+++ b/src/soc/intel/skylake/memmap.c</span><br><span>@@ -122,7 +122,7 @@</span><br><span> </span><br><span> /* GDXC MOT */</span><br><span> tracehub_base -= GDXC_MOT_MEMORY_SIZE;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Round down to natual boundary accroding to PSMI size */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Round down to natural boundary according to PSMI size */</span><br><span> tracehub_base = ALIGN_DOWN(tracehub_base, PSMI_BUFFER_AREA_SIZE);</span><br><span> /* GDXC IOT */</span><br><span> tracehub_base -= GDXC_IOT_MEMORY_SIZE;</span><br><span>diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c</span><br><span>index 8f2fb33..a262462 100644</span><br><span>--- a/src/soc/intel/skylake/romstage/systemagent.c</span><br><span>+++ b/src/soc/intel/skylake/romstage/systemagent.c</span><br><span>@@ -34,12 +34,12 @@</span><br><span> { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Fixed MMIO addresss into PCI configuration space */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Fixed MMIO address into PCI configuration space */</span><br><span> sa_set_pci_bar(soc_fixed_pci_resources,</span><br><span> ARRAY_SIZE(soc_fixed_pci_resources));</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Fixed MMIO addresss into MCH base address */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Fixed MMIO address into MCH base address */</span><br><span> sa_set_mch_bar(soc_fixed_mch_resources,</span><br><span> ARRAY_SIZE(soc_fixed_mch_resources));</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable PAM regisers */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable PAM registers */</span><br><span> enable_pam_region();</span><br><span> }</span><br><span>diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c</span><br><span>index 8af995d..3227519 100644</span><br><span>--- a/src/soc/intel/skylake/systemagent.c</span><br><span>+++ b/src/soc/intel/skylake/systemagent.c</span><br><span>@@ -28,7 +28,7 @@</span><br><span> /*</span><br><span> * SoC implementation</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Add all known fixed memory ranges for Host Controller/Mmeory</span><br><span style="color: hsl(120, 100%, 40%);">+ * Add all known fixed memory ranges for Host Controller/Memory</span><br><span> * controller.</span><br><span> */</span><br><span> void soc_add_fixed_mmio_resources(struct device *dev, int *index)</span><br><span>diff --git a/src/soc/marvell/mvmap2315/pmic.c b/src/soc/marvell/mvmap2315/pmic.c</span><br><span>index 89ea5eb..f9fcfc8 100644</span><br><span>--- a/src/soc/marvell/mvmap2315/pmic.c</span><br><span>+++ b/src/soc/marvell/mvmap2315/pmic.c</span><br><span>@@ -92,12 +92,12 @@</span><br><span> </span><br><span> void no_boot(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /*TODO: impelement no_boot */</span><br><span style="color: hsl(120, 100%, 40%);">+ /*TODO: implement no_boot */</span><br><span> }</span><br><span> </span><br><span> void charging_screen(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /*TODO: impelement charging_screen */</span><br><span style="color: hsl(120, 100%, 40%);">+ /*TODO: implement charging_screen */</span><br><span> }</span><br><span> </span><br><span> void full_boot(void)</span><br><span>diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c</span><br><span>index 7b6444d..8fb839d 100644</span><br><span>--- a/src/soc/nvidia/tegra210/romstage.c</span><br><span>+++ b/src/soc/nvidia/tegra210/romstage.c</span><br><span>@@ -60,7 +60,7 @@</span><br><span> * Trust Zone needs to be initialized after the DRAM initialization</span><br><span> * because carveout registers are programmed during DRAM init.</span><br><span> * cbmem_initialize() is dependent on the Trust Zone region</span><br><span style="color: hsl(0, 100%, 40%);">- * initalization because CBMEM lives right below the Trust Zone which</span><br><span style="color: hsl(120, 100%, 40%);">+ * initialization because CBMEM lives right below the Trust Zone which</span><br><span> * needs to be properly identified.</span><br><span> */</span><br><span> trustzone_region_init();</span><br><span>diff --git a/src/soc/qualcomm/ipq40xx/blobs_init.c b/src/soc/qualcomm/ipq40xx/blobs_init.c</span><br><span>index 77c0289..2b5e1fd 100644</span><br><span>--- a/src/soc/qualcomm/ipq40xx/blobs_init.c</span><br><span>+++ b/src/soc/qualcomm/ipq40xx/blobs_init.c</span><br><span>@@ -108,7 +108,7 @@</span><br><span> die("Fail to Initialize DDR\n");</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Once DDR initializer finished, its verison can be found at a fixed</span><br><span style="color: hsl(120, 100%, 40%);">+ * Once DDR initializer finished, its version can be found at a fixed</span><br><span> * address in SRAM.</span><br><span> */</span><br><span> printk(BIOS_INFO, "DDR version %.*s initialized\n",</span><br><span>diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c</span><br><span>index 5b19fc1..9549e9a 100644</span><br><span>--- a/src/soc/qualcomm/ipq806x/blobs_init.c</span><br><span>+++ b/src/soc/qualcomm/ipq806x/blobs_init.c</span><br><span>@@ -80,7 +80,7 @@</span><br><span> die("Fail to Initialize DDR\n");</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Once DDR initializer finished, its verison can be found at a fixed</span><br><span style="color: hsl(120, 100%, 40%);">+ * Once DDR initializer finished, its version can be found at a fixed</span><br><span> * address in SRAM.</span><br><span> */</span><br><span> printk(BIOS_INFO, "DDR version %.*s initialized\n",</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23706">change 23706</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23706"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6 </div>
<div style="display:none"> Gerrit-Change-Number: 23706 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer@gmx.net> </div>