[coreboot-gerrit] Change in coreboot[master]: drivers/intel/gma: fix opregion SCI register for Atom platforms

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/23696


Change subject: drivers/intel/gma: fix opregion SCI register for Atom platforms
......................................................................

drivers/intel/gma: fix opregion SCI register for Atom platforms

Most Intel platforms use separate registers for software-based
SMI (0xe0) and SCI (0xe8), but Atom-based platforms use a single
combined register (0xe0) for both. Adjust opregion implementation
to use the correct register for Atom-based platforms.

Test: Boot Windows on Atom-based ChromeOS device with Tianocore
payload and non-VBIOS graphics init; observe Intel display
driver loaded correctly and internal display not blank.

Change-Id: I636986226ff951dae637dca5bc3ad0e023d94243
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/gma/opregion.h
2 files changed, 15 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/23696/1

diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c
index 74c629c..4565173 100644
--- a/src/drivers/intel/gma/opregion.c
+++ b/src/drivers/intel/gma/opregion.c
@@ -32,6 +32,7 @@
 {
 	device_t igd;
 	u16 reg16;
+	u16 sci;
 
 	igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
 	if (!igd || !igd->enabled)
@@ -44,14 +45,25 @@
 	pci_write_config32(igd, ASLS, opregion);
 
 	/*
+	 * Atom-based platforms use a combined SMI/SCI register,
+	 * whereas non-Atom platforms use a separate SCI register
+	 */
+	if (IS_ENABLED(CONFIG_SOC_INTEL_BAYTRAIL) ||
+			IS_ENABLED(CONFIG_SOC_INTEL_BRASWELL) ||
+			IS_ENABLED(CONFIG_SOC_INTEL_APOLLOLAKE))
+		sci = SWSMISCI;
+	else
+		sci = SWSCI;
+
+	/*
 	 * Intel's Windows driver relies on this:
 	 * Intel BIOS Specification
 	 * Chapter 5.4 "ASL Software SCI Handler"
 	 */
-	reg16 = pci_read_config16(igd, SWSCI);
+	reg16 = pci_read_config16(igd, sci);
 	reg16 &= ~GSSCIE;
 	reg16 |= SMISCISEL;
-	pci_write_config16(igd, SWSCI, reg16);
+	pci_write_config16(igd, sci, reg16);
 }
 
 /* Restore ASLS register on S3 resume and prepare SWSCI. */
diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h
index 3ae68e5..8ef3dcf 100644
--- a/src/drivers/intel/gma/opregion.h
+++ b/src/drivers/intel/gma/opregion.h
@@ -25,6 +25,7 @@
 /* IGD PCI Configuration register */
 #define ASLS           0xfc            /* OpRegion Base */
 #define SWSCI          0xe8            /* SWSCI Register */
+#define SWSMISCI       0xe0            /* SWSMISCI Register */
 #define GSSCIE         (1 << 0)        /* SCI Event trigger */
 #define SMISCISEL      (1 << 15)       /* Select SMI or SCI event source */
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I636986226ff951dae637dca5bc3ad0e023d94243
Gerrit-Change-Number: 23696
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
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