[coreboot-gerrit] Change in coreboot[master]: intel/fsp: Update cannonlake fsp header
Lijian Zhao (Code Review)
gerrit at coreboot.org
Fri Feb 9 22:07:08 CET 2018
Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/23677
Change subject: intel/fsp: Update cannonlake fsp header
......................................................................
intel/fsp: Update cannonlake fsp header
Update Cannonlake FSP header to revision 7.x.25.31. Following changes
had been made:
TBD
TEST=NONE
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6
---
M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
A src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h
M src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h
4 files changed, 207 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/23677/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
index d504f96..d014f81 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
@@ -474,9 +474,21 @@
**/
UINT8 CpuTraceHubMemReg1Size;
-/** Offset 0x00F6
+/** Offset 0x00F6 - Enable or Disable Peci C10 Reset command
+ Enable or Disable Peci C10 Reset command; <b>0: Disable;</b> 1: Enable.
+ $EN_DIS
**/
- UINT8 UnusedUpdSpace3[6];
+ UINT8 PeciC10Reset;
+
+/** Offset 0x00F7 - Enable or Disable Peci Sx Reset command
+ Enable or Disable Peci Sx Reset command; <b>0: Disable;</b> 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PeciSxReset;
+
+/** Offset 0x00F8
+**/
+ UINT8 UnusedUpdSpace3[4];
/** Offset 0x00FC - Enable Intel HD Audio (Azalia)
0: Disable, 1: Enable (Default) Azalia controller
@@ -691,9 +703,24 @@
**/
UINT8 DmiGen3RxCtlePeaking[4];
-/** Offset 0x0144
+/** Offset 0x0144 - Thermal Velocity Boost Ratio clipping
+ 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction
+ caused by high package temperatures for processors that implement the Intel Thermal
+ Velocity Boost (TVB) feature
+ 0: Disabled, 1: Enabled
**/
- UINT8 UnusedUpdSpace6[4];
+ UINT8 TvbRatioClipping;
+
+/** Offset 0x0145 - Thermal Velocity Boost voltage optimization
+ 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations
+ for processors that implement the Intel Thermal Velocity Boost (TVB) feature.
+ 0: Disabled, 1: Enabled
+**/
+ UINT8 TvbVoltageOptimization;
+
+/** Offset 0x0146
+**/
+ UINT8 UnusedUpdSpace6[2];
/** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control
Range: 0-15, 12 is default for each bundle, must be specified based upon platform design
@@ -1374,8 +1401,8 @@
**/
UINT8 PchSmbAlertEnable;
-/** Offset 0x0463 - ReservedSecurityPreMem
- Reserved for Security Pre-Mem
+/** Offset 0x0463 - ReservedPchPreMem
+ Reserved for Pch Pre-Mem
$EN_DIS
**/
UINT8 ReservedPchPreMem[13];
@@ -2428,7 +2455,7 @@
**/
UINT8 Gen3SwEqEnableVocTest;
-/** Offset 0x0537 - PPCIe Rx Compliance Testing Mode
+/** Offset 0x0537 - PCIe Rx Compliance Testing Mode
Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1):
PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode;
it should only be set when doing PCIe compliance testing
@@ -2522,7 +2549,7 @@
/** Offset 0x0583 - BdatTestType
Indicates the type of Memory Training data to populate into the BDAT ACPI table.
- 0:Rank Marign Tool, 1:Margin2D
+ 0:Rank Margin Tool, 1:Margin2D
**/
UINT8 BdatTestType;
@@ -2542,11 +2569,17 @@
**/
UINT16 BiosSize;
-/** Offset 0x0594 - SecurityTestRsvd
+/** Offset 0x0594 - TxtAcheckRequest
+ Enable/Disable. When Enabled, it will forcing calling TXT Acheck once.
+ $EN_DIS
+**/
+ UINT8 TxtAcheckRequest;
+
+/** Offset 0x0595 - SecurityTestRsvd
Reserved for SA Pre-Mem Test
$EN_DIS
**/
- UINT8 SecurityTestRsvd[4];
+ UINT8 SecurityTestRsvd[3];
/** Offset 0x0598 - Smbus dynamic power gating
Disable or Enable Smbus dynamic power gating.
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
index 0285dd1..0f3577a 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
@@ -1093,15 +1093,22 @@
**/
UINT16 ImonSlope1[5];
-/** Offset 0x0324 - ReservedCpuPostMemProduction
+/** Offset 0x0324 - CPU VR Power Delivery Design
+ Used to communicate the power delivery design capability of the board. This value
+ is an enum of the available power delivery segments that are defined in the Platform
+ Design Guide.
+**/
+ UINT32 VrPowerDeliveryDesign;
+
+/** Offset 0x0328 - ReservedCpuPostMemProduction
Reserved for CPU Post-Mem Production
$EN_DIS
**/
UINT8 ReservedCpuPostMemProduction[1];
-/** Offset 0x0325
+/** Offset 0x0329
**/
- UINT8 UnusedUpdSpace10[33];
+ UINT8 UnusedUpdSpace10[29];
/** Offset 0x0346 - Enable DMI ASPM
Deprecated.
@@ -1869,7 +1876,6 @@
0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5
pads termination respectively. One byte for each controller, byte0 for I2C0, byte1
for I2C1, and so on.
- 0x1:None, 0x13:1kOhm WPU, 0x15:5kOhm WPU, 0x19:20kOhm WPU
**/
UINT8 PchSerialIoI2cPadsTermination[6];
@@ -2283,7 +2289,7 @@
**/
UINT8 ChapDeviceEnable;
-/** Offset 0x07B2 - Skip PAM regsiter lock
+/** Offset 0x07B2 - Skip PAM register lock
Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
PAM registers will be locked by RC
$EN_DIS
@@ -2830,9 +2836,10 @@
**/
UINT16 PsysPmax;
-/** Offset 0x0858
+/** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0
+ Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF
**/
- UINT8 Reserved0[2];
+ UINT16 CstateLatencyControl0Irtl;
/** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1
Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF
@@ -3074,8 +3081,7 @@
UINT8 PchUnlockGpioPads;
/** Offset 0x08C2 - PCH Unlock SBI access
- This unlock the SBI lock bit to allow SBI after post time. 0: Lock SBI access; 1:
- Unlock SBI access.
+ Deprecated
$EN_DIS
**/
UINT8 PchSbiUnlock;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h
new file mode 100644
index 0000000..eeba7ae
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h
@@ -0,0 +1,136 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPTUPD_H__
+#define __FSPTUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+/** Fsp T Core UPD
+**/
+typedef struct {
+
+/** Offset 0x0020
+**/
+ UINT32 MicrocodeRegionBase;
+
+/** Offset 0x0024
+**/
+ UINT32 MicrocodeRegionSize;
+
+/** Offset 0x0028
+**/
+ UINT32 CodeRegionBase;
+
+/** Offset 0x002C
+**/
+ UINT32 CodeRegionSize;
+
+/** Offset 0x0030
+**/
+ UINT8 Reserved[16];
+} FSPT_CORE_UPD;
+
+/** Fsp T Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - PcdSerialIoUartDebugEnable
+ Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
+ 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
+**/
+ UINT8 PcdSerialIoUartDebugEnable;
+
+/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT
+ Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
+ Core interface, it cannot be used for debug purpose.
+ 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+ UINT8 PcdSerialIoUartNumber;
+
+/** Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT
+ Select SerialIo Uart0 pin muxing. Setting valid only if PcdSerialIoUartNumber is
+ set to UART0.
+ 0:default pins, 1:pins muxed with CNV_BRI/RGI
+**/
+ UINT8 PcdSerialIoUart0PinMuxing;
+
+/** Offset 0x0043
+**/
+ UINT8 UnusedUpdSpace0;
+
+/** Offset 0x0044
+**/
+ UINT32 PcdSerialIoUartInputClock;
+
+/** Offset 0x0048 - Pci Express Base Address
+ Base address to be programmed for Pci Express
+**/
+ UINT64 PcdPciExpressBaseAddress;
+
+/** Offset 0x0050 - Pci Express Region Length
+ Region Length to be programmed for Pci Express
+**/
+ UINT32 PcdPciExpressRegionLength;
+
+/** Offset 0x0054
+**/
+ UINT8 ReservedFsptUpd1[44];
+} FSP_T_CONFIG;
+
+/** Fsp T UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPT_CORE_UPD FsptCoreUpd;
+
+/** Offset 0x0040
+**/
+ FSP_T_CONFIG FsptConfig;
+
+/** Offset 0x0080
+**/
+ UINT16 UpdTerminator;
+} FSPT_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h
index 435eccb..941a891 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h
@@ -84,6 +84,19 @@
} SiMrcVersion;
//
+// Matches MrcChannelSts enum in MRC
+//
+#ifndef CHANNEL_NOT_PRESENT
+#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
+#endif
+#ifndef CHANNEL_DISABLED
+#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
+#endif
+#ifndef CHANNEL_PRESENT
+#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
+#endif
+
+//
// Matches MrcDimmSts enum in MRC
//
#ifndef DIMM_ENABLED
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6
Gerrit-Change-Number: 23677
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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