<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23677">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/fsp: Update cannonlake fsp header<br><br>Update Cannonlake FSP header to revision 7.x.25.31. Following changes<br>had been made:<br>TBD<br><br>TEST=NONE<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br><br>Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6<br>---<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h<br>A src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h<br>4 files changed, 207 insertions(+), 19 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/23677/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h</span><br><span>index d504f96..d014f81 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h</span><br><span>@@ -474,9 +474,21 @@</span><br><span> **/</span><br><span> UINT8 CpuTraceHubMemReg1Size;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x00F6</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00F6 - Enable or Disable Peci C10 Reset command</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Peci C10 Reset command; <b>0: Disable;</b> 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace3[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PeciC10Reset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00F7 - Enable or Disable Peci Sx Reset command</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Peci Sx Reset command; <b>0: Disable;</b> 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PeciSxReset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00F8</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace3[4];</span><br><span> </span><br><span> /** Offset 0x00FC - Enable Intel HD Audio (Azalia)</span><br><span> 0: Disable, 1: Enable (Default) Azalia controller</span><br><span>@@ -691,9 +703,24 @@</span><br><span> **/</span><br><span> UINT8 DmiGen3RxCtlePeaking[4];</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0144</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0144 - Thermal Velocity Boost Ratio clipping</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction</span><br><span style="color: hsl(120, 100%, 40%);">+ caused by high package temperatures for processors that implement the Intel Thermal</span><br><span style="color: hsl(120, 100%, 40%);">+ Velocity Boost (TVB) feature</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disabled, 1: Enabled</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace6[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TvbRatioClipping;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0145 - Thermal Velocity Boost voltage optimization</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations</span><br><span style="color: hsl(120, 100%, 40%);">+ for processors that implement the Intel Thermal Velocity Boost (TVB) feature.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disabled, 1: Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TvbVoltageOptimization;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0146</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace6[2];</span><br><span> </span><br><span> /** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control</span><br><span> Range: 0-15, 12 is default for each bundle, must be specified based upon platform design</span><br><span>@@ -1374,8 +1401,8 @@</span><br><span> **/</span><br><span> UINT8 PchSmbAlertEnable;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0463 - ReservedSecurityPreMem</span><br><span style="color: hsl(0, 100%, 40%);">- Reserved for Security Pre-Mem</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0463 - ReservedPchPreMem</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved for Pch Pre-Mem</span><br><span> $EN_DIS</span><br><span> **/</span><br><span> UINT8 ReservedPchPreMem[13];</span><br><span>@@ -2428,7 +2455,7 @@</span><br><span> **/</span><br><span> UINT8 Gen3SwEqEnableVocTest;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0537 - PPCIe Rx Compliance Testing Mode</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0537 - PCIe Rx Compliance Testing Mode</span><br><span> Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1):</span><br><span> PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode;</span><br><span> it should only be set when doing PCIe compliance testing</span><br><span>@@ -2522,7 +2549,7 @@</span><br><span> </span><br><span> /** Offset 0x0583 - BdatTestType</span><br><span> Indicates the type of Memory Training data to populate into the BDAT ACPI table.</span><br><span style="color: hsl(0, 100%, 40%);">- 0:Rank Marign Tool, 1:Margin2D</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Rank Margin Tool, 1:Margin2D</span><br><span> **/</span><br><span> UINT8 BdatTestType;</span><br><span> </span><br><span>@@ -2542,11 +2569,17 @@</span><br><span> **/</span><br><span> UINT16 BiosSize;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0594 - SecurityTestRsvd</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0594 - TxtAcheckRequest</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. When Enabled, it will forcing calling TXT Acheck once.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TxtAcheckRequest;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0595 - SecurityTestRsvd</span><br><span> Reserved for SA Pre-Mem Test</span><br><span> $EN_DIS</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SecurityTestRsvd[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SecurityTestRsvd[3];</span><br><span> </span><br><span> /** Offset 0x0598 - Smbus dynamic power gating</span><br><span> Disable or Enable Smbus dynamic power gating.</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h</span><br><span>index 0285dd1..0f3577a 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h</span><br><span>@@ -1093,15 +1093,22 @@</span><br><span> **/</span><br><span> UINT16 ImonSlope1[5];</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0324 - ReservedCpuPostMemProduction</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0324 - CPU VR Power Delivery Design</span><br><span style="color: hsl(120, 100%, 40%);">+ Used to communicate the power delivery design capability of the board. This value</span><br><span style="color: hsl(120, 100%, 40%);">+ is an enum of the available power delivery segments that are defined in the Platform</span><br><span style="color: hsl(120, 100%, 40%);">+ Design Guide.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 VrPowerDeliveryDesign;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0328 - ReservedCpuPostMemProduction</span><br><span> Reserved for CPU Post-Mem Production</span><br><span> $EN_DIS</span><br><span> **/</span><br><span> UINT8 ReservedCpuPostMemProduction[1];</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0325</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0329</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace10[33];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace10[29];</span><br><span> </span><br><span> /** Offset 0x0346 - Enable DMI ASPM</span><br><span> Deprecated.</span><br><span>@@ -1869,7 +1876,6 @@</span><br><span> 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5</span><br><span> pads termination respectively. One byte for each controller, byte0 for I2C0, byte1</span><br><span> for I2C1, and so on.</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1:None, 0x13:1kOhm WPU, 0x15:5kOhm WPU, 0x19:20kOhm WPU</span><br><span> **/</span><br><span> UINT8 PchSerialIoI2cPadsTermination[6];</span><br><span> </span><br><span>@@ -2283,7 +2289,7 @@</span><br><span> **/</span><br><span> UINT8 ChapDeviceEnable;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07B2 - Skip PAM regsiter lock</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07B2 - Skip PAM register lock</span><br><span> Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):</span><br><span> PAM registers will be locked by RC</span><br><span> $EN_DIS</span><br><span>@@ -2830,9 +2836,10 @@</span><br><span> **/</span><br><span> UINT16 PsysPmax;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0858</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Reserved0[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 CstateLatencyControl0Irtl;</span><br><span> </span><br><span> /** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1</span><br><span> Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF</span><br><span>@@ -3074,8 +3081,7 @@</span><br><span> UINT8 PchUnlockGpioPads;</span><br><span> </span><br><span> /** Offset 0x08C2 - PCH Unlock SBI access</span><br><span style="color: hsl(0, 100%, 40%);">- This unlock the SBI lock bit to allow SBI after post time. 0: Lock SBI access; 1:</span><br><span style="color: hsl(0, 100%, 40%);">- Unlock SBI access.</span><br><span style="color: hsl(120, 100%, 40%);">+ Deprecated</span><br><span> $EN_DIS</span><br><span> **/</span><br><span> UINT8 PchSbiUnlock;</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h</span><br><span>new file mode 100644</span><br><span>index 0000000..eeba7ae</span><br><span>--- /dev/null</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h</span><br><span>@@ -0,0 +1,136 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/** @file</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Redistribution and use in source and binary forms, with or without modification,</span><br><span style="color: hsl(120, 100%, 40%);">+are permitted provided that the following conditions are met:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions of source code must retain the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer.</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions in binary form must reproduce the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer in the documentation and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ other materials provided with the distribution.</span><br><span style="color: hsl(120, 100%, 40%);">+* Neither the name of Intel Corporation nor the names of its contributors may</span><br><span style="color: hsl(120, 100%, 40%);">+ be used to endorse or promote products derived from this software without</span><br><span style="color: hsl(120, 100%, 40%);">+ specific prior written permission.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"</span><br><span style="color: hsl(120, 100%, 40%);">+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span><br><span style="color: hsl(120, 100%, 40%);">+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span><br><span style="color: hsl(120, 100%, 40%);">+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE</span><br><span style="color: hsl(120, 100%, 40%);">+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span><br><span style="color: hsl(120, 100%, 40%);">+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF</span><br><span style="color: hsl(120, 100%, 40%);">+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS</span><br><span style="color: hsl(120, 100%, 40%);">+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN</span><br><span style="color: hsl(120, 100%, 40%);">+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)</span><br><span style="color: hsl(120, 100%, 40%);">+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF</span><br><span style="color: hsl(120, 100%, 40%);">+ THE POSSIBILITY OF SUCH DAMAGE.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ This file is automatically generated. Please do NOT modify !!!</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __FSPTUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __FSPTUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <FspUpd.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack(1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp T Core UPD</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0020</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 MicrocodeRegionBase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0024</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 MicrocodeRegionSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0028</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 CodeRegionBase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x002C</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 CodeRegionSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0030</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Reserved[16];</span><br><span style="color: hsl(120, 100%, 40%);">+} FSPT_CORE_UPD;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp T Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0040 - PcdSerialIoUartDebugEnable</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. </span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcdSerialIoUartDebugEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT</span><br><span style="color: hsl(120, 100%, 40%);">+ Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT</span><br><span style="color: hsl(120, 100%, 40%);">+ Core interface, it cannot be used for debug purpose.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcdSerialIoUartNumber;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT</span><br><span style="color: hsl(120, 100%, 40%);">+ Select SerialIo Uart0 pin muxing. Setting valid only if PcdSerialIoUartNumber is</span><br><span style="color: hsl(120, 100%, 40%);">+ set to UART0.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:default pins, 1:pins muxed with CNV_BRI/RGI</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcdSerialIoUart0PinMuxing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0043</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0044</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PcdSerialIoUartInputClock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0048 - Pci Express Base Address</span><br><span style="color: hsl(120, 100%, 40%);">+ Base address to be programmed for Pci Express </span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 PcdPciExpressBaseAddress;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0050 - Pci Express Region Length</span><br><span style="color: hsl(120, 100%, 40%);">+ Region Length to be programmed for Pci Express </span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PcdPciExpressRegionLength;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0054</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFsptUpd1[44];</span><br><span style="color: hsl(120, 100%, 40%);">+} FSP_T_CONFIG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp T UPD Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0000</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_UPD_HEADER FspUpdHeader;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0020</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSPT_CORE_UPD FsptCoreUpd;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0040</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_T_CONFIG FsptConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0080</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 UpdTerminator;</span><br><span style="color: hsl(120, 100%, 40%);">+} FSPT_UPD;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h</span><br><span>index 435eccb..941a891 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h</span><br><span>@@ -84,6 +84,19 @@</span><br><span> } SiMrcVersion;</span><br><span> </span><br><span> //</span><br><span style="color: hsl(120, 100%, 40%);">+// Matches MrcChannelSts enum in MRC</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CHANNEL_NOT_PRESENT</span><br><span style="color: hsl(120, 100%, 40%);">+#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CHANNEL_DISABLED</span><br><span style="color: hsl(120, 100%, 40%);">+#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CHANNEL_PRESENT</span><br><span style="color: hsl(120, 100%, 40%);">+#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//</span><br><span> // Matches MrcDimmSts enum in MRC</span><br><span> //</span><br><span> #ifndef DIMM_ENABLED</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23677">change 23677</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23677"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6 </div>
<div style="display:none"> Gerrit-Change-Number: 23677 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>