[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Update GPIO ASL

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/23664


Change subject: soc/intel/cannonlake: Update GPIO ASL
......................................................................

soc/intel/cannonlake: Update GPIO ASL

GPIO pin definition had been updated to match Cannonlake PCH-LP EDS,
hence the ACPI dsdt table will include those changes as well.

BUG=None
TEST=Build coreboot image, flah coreboot image into DUT, and target
system can boot up into OS.

Change-Id: I958e0cb71b4e656bec9bfe2d12076b577b57629b
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/acpi/gpio.asl
1 file changed, 32 insertions(+), 5 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/23664/1

diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl
index c2bf8d9..8a990b3 100644
--- a/src/soc/intel/cannonlake/acpi/gpio.asl
+++ b/src/soc/intel/cannonlake/acpi/gpio.asl
@@ -28,6 +28,8 @@
 	{
 		Memory32Fixed (ReadWrite, 0, 0, COM0)
 		Memory32Fixed (ReadWrite, 0, 0, COM1)
+		Memory32Fixed (ReadWrite, 0, 0, COM2)
+		Memory32Fixed (ReadWrite, 0, 0, COM3)
 		Memory32Fixed (ReadWrite, 0, 0, COM4)
 		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
 			{ GPIO_IRQ14 }
@@ -47,11 +49,24 @@
 		Store (^^PCRB (PID_GPIOCOM1), BAS1)
 		Store (GPIO_BASE_SIZE, LEN1)
 
+		/* GPIO Community 2 */
+		CreateDWordField (^RBUF, ^COM2._BAS, BAS2)
+		CreateDWordField (^RBUF, ^COM2._LEN, LEN2)
+		Store (^^PCRB (PID_GPIOCOM2), BAS2)
+		Store (GPIO_BASE_SIZE, LEN2)
+
+		/* GPIO Community 3 */
+		CreateDWordField (^RBUF, ^COM3._BAS, BAS3)
+		CreateDWordField (^RBUF, ^COM3._LEN, LEN3)
+		Store (^^PCRB (PID_GPIOCOM3), BAS3)
+		Store (GPIO_BASE_SIZE, LEN3)
+
+
 		/* GPIO Community 4 */
 		CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
-		CreateDWordField (^RBUF, ^COM4._LEN, LEN3)
+		CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
 		Store (^^PCRB (PID_GPIOCOM4), BAS4)
-		Store (GPIO_BASE_SIZE, LEN3)
+		Store (GPIO_BASE_SIZE, LEN4)
 
 		Return (RBUF)
 	}
@@ -69,19 +84,31 @@
 Method (GADD, 1, NotSerialized)
 {
 	/* GPIO Community 0 */
-	If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_G7)))
+	If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPIO_RSVD_11)))
 	{
 		Store (PID_GPIOCOM0, Local0)
 		Subtract (Arg0, GPP_A0, Local1)
 	}
 	/* GPIO Community 1 */
-	If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, GPP_H23)))
+	If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, GPIO_RSVD_52)))
 	{
 		Store (PID_GPIOCOM1, Local0)
 		Subtract (Arg0, GPP_D0, Local1)
 	}
+	/* GPIO Community 2 */
+	If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, GPD11)))
+	{
+		Store (PID_GPIOCOM1, Local0)
+		Subtract (Arg0, GPD0, Local1)
+	}
+	/* GPIO Community 3 */
+	If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_78)))
+	{
+		Store (PID_GPIOCOM1, Local0)
+		Subtract (Arg0, HDA_BCLK, Local1)
+	}
 	/* GPIO Community 04*/
-	If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_E23)))
+	If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPIO_RSVD_67)))
 	{
 		Store (PID_GPIOCOM4, Local0)
 		Subtract (Arg0, GPP_C0, Local1)

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I958e0cb71b4e656bec9bfe2d12076b577b57629b
Gerrit-Change-Number: 23664
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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