[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82801gx: Automatically handle disabling functions
Arthur Heymans (Code Review)
gerrit at coreboot.org
Thu Feb 8 22:10:11 CET 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23662
Change subject: sb/intel/i82801gx: Automatically handle disabling functions
......................................................................
sb/intel/i82801gx: Automatically handle disabling functions
Disable functions based on the devicetree and implement pcie port
coalescing to handle cases when the first PCIe port is disabled.
TODO:
* check if devicetrees matched removed FD writes in romstage
* check if it actually works on hardware
Change-Id: I2f6f270c631b97ececf1bd3c23f19b27828e6885
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/apple/macbook21/romstage.c
M src/mainboard/asrock/g41c-gs/romstage.c
M src/mainboard/asus/p5gc-mx/romstage.c
M src/mainboard/foxconn/g41s-k/romstage.c
M src/mainboard/getac/p470/romstage.c
M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
M src/mainboard/ibase/mb899/devicetree.cb
M src/mainboard/ibase/mb899/romstage.c
M src/mainboard/intel/d510mo/romstage.c
M src/mainboard/intel/d945gclf/romstage.c
M src/mainboard/kontron/986lcd-m/romstage.c
M src/mainboard/lenovo/t60/romstage.c
M src/mainboard/lenovo/x60/romstage.c
M src/mainboard/lenovo/z61t/romstage.c
M src/mainboard/roda/rk886ex/romstage.c
M src/southbridge/intel/i82801gx/chip.h
M src/southbridge/intel/i82801gx/i82801gx.c
M src/southbridge/intel/i82801gx/i82801gx.h
19 files changed, 99 insertions(+), 81 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/23662/1
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index 79cc35d..3dc62e2 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -169,11 +169,6 @@
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
- /* Disable unused devices */
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN
- | FD_ACMOD | FD_ACAUD;
- RCBA32(FD) |= (1 << 0); /* Required. */
-
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
/* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index 4498b10..ff09ce8 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -64,8 +64,6 @@
reg32 = RCBA32(GCS);
reg32 |= (1 << 5);
RCBA32(GCS) = reg32;
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
- | FD_ACAUD | 1;
RCBA32(CG) = 0x00000001;
}
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index e1725d0..53d4546 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -123,10 +123,6 @@
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
- /* Disable unused devices */
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
- | FD_ACAUD | 1;
-
/* Enable PCIe Root Port Clock Gate */
RCBA32(CG) = 0x00000001;
}
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c
index 5ea41ea..2aded61 100644
--- a/src/mainboard/foxconn/g41s-k/romstage.c
+++ b/src/mainboard/foxconn/g41s-k/romstage.c
@@ -66,8 +66,6 @@
RCBA8(OIC) = 0x03;
RCBA8(OIC);
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN |
- FD_ACMOD | FD_ACAUD | FD_PATA | 1;
RCBA32(CG) = 0x00000001;
}
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index e58ef1b..42bc8bc 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -166,10 +166,6 @@
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
- /* Disable unused devices */
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;
- RCBA32(FD) |= (1 << 0); // Required.
-
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
index 926a5a7..aecac08 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -86,9 +86,6 @@
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
- /* Disable unused devices */
- RCBA32(FD) = 0x003c0061;
-
/* Enable PCIe Root Port Clock Gate */
RCBA32(CG) = 0x00000001;
}
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index ac336e4..fb70134 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -103,8 +103,6 @@
RCBA8(OIC);
RCBA32(GCS) = 0x00190464;
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
- | FD_ACAUD | 1;
RCBA32(CG) = 0x00000000;
RCBA32(0x3430) = 0x00000001;
RCBA32(0x3e00) = 0xff000001;
diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb
index c63e5d6..06d25be 100644
--- a/src/mainboard/ibase/mb899/devicetree.cb
+++ b/src/mainboard/ibase/mb899/devicetree.cb
@@ -41,6 +41,8 @@
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"
+ register "pcie_port_coalesce" = "1"
+
#device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe
device pci 1c.1 on end # PCIe
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 0d3b839..dd991d9 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -190,7 +190,6 @@
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index b2044c1..afea7f2 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -83,10 +83,6 @@
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
-
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD
- | FD_PATA;
- RCBA32(FD) |= 1;
}
void mainboard_romstage_entry(unsigned long bist)
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 27c1e3e..b316ed0 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -66,12 +66,6 @@
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
- /* Disable unused devices */
- // FIXME devicetree disables pcie3 not 2.
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE2 | (1 << 10) | FD_INTLAN
- | FD_ACMOD | FD_ACAUD;
- RCBA32(FD) |= 1;
-
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
}
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index f7e8131..6770b2f 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -202,23 +202,7 @@
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
- /* Now, this is a bit ugly. As per PCI specification, function 0 of a
- * device always has to be implemented. So disabling ethernet port 1
- * would essentially disable all three ethernet ports of the mainboard.
- * It's possible to rename the ports to achieve compatibility to the
- * PCI spec but this will confuse all (static!) tables containing
- * interrupt routing information.
- * To avoid this, we enable (unused) port 6 and swap it with port 1
- * in the case that ethernet port 1 is disabled. Since no devices
- * are connected to that port, we don't have to worry about interrupt
- * routing.
- */
- int port_shuffle = 0;
-
/* Disable unused devices */
- reg32 = FD_ACMOD|FD_ACAUD|FD_PATA;
- reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4;
-
if (read_option(ethernet1, 0) != 0) {
printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n");
reg32 |= FD_PCIE1;
@@ -226,23 +210,10 @@
if (read_option(ethernet2, 0) != 0) {
printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n");
reg32 |= FD_PCIE2;
- } else {
- if (reg32 & FD_PCIE1)
- port_shuffle = 1;
}
if (read_option(ethernet3, 0) != 0) {
printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n");
reg32 |= FD_PCIE3;
- } else {
- if (reg32 & FD_PCIE1)
- port_shuffle = 1;
- }
-
- if (port_shuffle) {
- /* Enable PCIE6 again */
- reg32 &= ~FD_PCIE6;
- /* Swap PCIE6 and PCIE1 */
- RCBA32(RPFN) = 0x00043215;
}
reg32 |= 1;
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 18470ea..ee5f4a5 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -100,10 +100,6 @@
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
- /* Disable unused devices */
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
- RCBA32(FD) |= (1 << 0); // Required.
-
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
RCBA32(0x1e84) = 0x00020001;
RCBA32(0x1e80) = 0x0000fe01;
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 0eac15a..7050645 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -99,10 +99,6 @@
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
- /* Disable unused devices */
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
- RCBA32(FD) |= (1 << 0); // Required.
-
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
RCBA32(0x1e84) = 0x00020001;
RCBA32(0x1e80) = 0x0000fe01;
diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c
index ffb72e3..8825d7d 100644
--- a/src/mainboard/lenovo/z61t/romstage.c
+++ b/src/mainboard/lenovo/z61t/romstage.c
@@ -100,10 +100,6 @@
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
- /* Disable unused devices */
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;
- RCBA32(FD) |= (1 << 0); // Required.
-
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
RCBA32(0x1e84) = 0x00020001;
RCBA32(IOTR0) = 0x0000fe01;
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index b4611f5..0e4adbc 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -134,11 +134,6 @@
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
- /* Disable unused devices */
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 |
- FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA;
- RCBA32(FD) |= (1 << 0); /* Required. */
-
/* This should probably go into the ACPI OS Init trap */
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h
index e89fcc4..a21a344 100644
--- a/src/southbridge/intel/i82801gx/chip.h
+++ b/src/southbridge/intel/i82801gx/chip.h
@@ -70,6 +70,10 @@
int docking_supported:1;
int p_cnt_throttling_supported:1;
int c3_latency;
+
+ /* Enable linear PCIe Root Port function numbers starting at zero */
+ int pcie_port_coalesce;
+
};
#endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */
diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c
index aab674b..b284876 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.c
+++ b/src/southbridge/intel/i82801gx/i82801gx.c
@@ -35,7 +35,98 @@
}
}
+static int i82801gx_function_disabled(const unsigned int busn,
+ const unsigned int devfn)
+{
+ const struct device *const dev = dev_find_slot(busn, devfn);
+ if (!dev) {
+ printk(BIOS_EMERG,
+ "PCI device %x:%x.%x"
+ " is not listed in devicetree. Disabling it\n",
+ busn, PCI_SLOT(devfn), PCI_FUNC(devfn));
+ return 1;
+ }
+ return !dev->enabled;
+}
+
+static void i82801gx_hide_functions(void)
+{
+ int i;
+ u32 reg32;
+
+ /* FIXME: This works pretty good if the devicetree is consistent. But
+ some functions have to be disabled in right order and/or have
+ other constraints. */
+
+ reg32 = RCBA32(FD);
+ struct {
+ int devfn;
+ u32 mask;
+ } functions[] = {
+ { PCI_DEVFN(0x1b, 0), FD_HDAUD }, /* HD Audio */
+ { PCI_DEVFN(0x1c, 0), FD_PCIE1 }, /* PCIe #1 */
+ { PCI_DEVFN(0x1c, 1), FD_PCIE2 }, /* PCIe #2 */
+ { PCI_DEVFN(0x1c, 2), FD_PCIE3 }, /* PCIe #3 */
+ { PCI_DEVFN(0x1c, 3), FD_PCIE4 }, /* PCIe #4 */
+ { PCI_DEVFN(0x1c, 4), FD_PCIE5 }, /* PCIe #5 */
+ { PCI_DEVFN(0x1c, 5), FD_PCIE6 }, /* PCIe #6 */
+ { PCI_DEVFN(0x1d, 0), FD_UHCI1234 }, /* UHCI #1 */
+ { PCI_DEVFN(0x1d, 1), FD_UHCI234 }, /* UHCI #2 */
+ { PCI_DEVFN(0x1d, 2), FD_UHCI34 }, /* UHCI #3 */
+ { PCI_DEVFN(0x1d, 3), FD_UHCI4 }, /* UHCI #3 */
+ { PCI_DEVFN(0x1d, 7), FD_EHCI }, /* EHCI #1 */
+ { PCI_DEVFN(0x1e, 2), FD_ACAUD }, /* AC ’97 Audio */
+ { PCI_DEVFN(0x1e, 3), FD_ACMOD }, /* AC ’97 Modem */
+ { PCI_DEVFN(0x1f, 0), FD_LPCB }, /* LPC */
+ { PCI_DEVFN(0x1f, 1), FD_PATA }, /* PATA */
+ { PCI_DEVFN(0x1f, 2), FD_SATA }, /* SATA */
+ { PCI_DEVFN(0x1f, 3), FD_SMBUS }, /* SMBus */
+ };
+ for (i = 0; i < ARRAY_SIZE(functions); ++i) {
+ if (i82801gx_function_disabled(0, functions[i].devfn))
+ reg32 |= functions[i].mask;
+ }
+
+ if (i82801gx_function_disabled(1, PCI_DEVFN(0x08, 0)))
+ reg32 |= FD_INTLAN;
+
+ RCBA32(FD) = reg32;
+ RCBA32(FD) |= (1 << 0); /* BIOS must write this... */
+}
+
+static void i82801gx_port_coalesing(
+ struct southbridge_intel_i82801gx_config *chip_info)
+{
+ int i;
+ u32 reg32 = 0;
+ int next_port = 0;
+
+ if (RCBA32(FD) & FD_PCIE1)
+ chip_info->pcie_port_coalesce = 1;
+
+ if (!chip_info->pcie_port_coalesce)
+ return;
+
+ for (i = 0; i < 6; i++) {
+ if (i82801gx_function_disabled(0, PCI_DEVFN(0x1c, i)))
+ continue;
+ reg32 |= next_port++ << (i * 4);
+ }
+
+ for (i = 0; i < 6; i++) {
+ if (i82801gx_function_disabled(0, PCI_DEVFN(0x1c, i)))
+ reg32 |= next_port++ << (i * 4);
+ }
+}
+
+static void i82801gx_init(void *chip_info)
+{
+ i82801gx_hide_functions();
+ i82801gx_port_coalesing(chip_info);
+}
+
struct chip_operations southbridge_intel_i82801gx_ops = {
CHIP_NAME("Intel ICH7/ICH7-M (82801Gx) Series Southbridge")
.enable_dev = i82801gx_enable,
+ .init = i82801gx_init,
};
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index df744fc..8f0c10f 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -290,8 +290,8 @@
* must know about it, too! */
#define FD_UHCI4 (1 << 11)
#define FD_UHCI34 ((1 << 10) | FD_UHCI4)
-#define FD_UHCI234 ((1 << 9) | FD_UHCI3)
-#define FD_UHCI1234 ((1 << 8) | FD_UHCI2)
+#define FD_UHCI234 ((1 << 9) | FD_UHCI34)
+#define FD_UHCI1234 ((1 << 8) | FD_UHCI234)
#define FD_INTLAN (1 << 7)
#define FD_ACMOD (1 << 6)
--
To view, visit https://review.coreboot.org/23662
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2f6f270c631b97ececf1bd3c23f19b27828e6885
Gerrit-Change-Number: 23662
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180208/0dbad7b4/attachment-0001.html>
More information about the coreboot-gerrit
mailing list