<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23662">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/i82801gx: Automatically handle disabling functions<br><br>Disable functions based on the devicetree and implement pcie port<br>coalescing to handle cases when the first PCIe port is disabled.<br><br>TODO:<br>* check if devicetrees matched removed FD writes in romstage<br>* check if it actually works on hardware<br><br>Change-Id: I2f6f270c631b97ececf1bd3c23f19b27828e6885<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/apple/macbook21/romstage.c<br>M src/mainboard/asrock/g41c-gs/romstage.c<br>M src/mainboard/asus/p5gc-mx/romstage.c<br>M src/mainboard/foxconn/g41s-k/romstage.c<br>M src/mainboard/getac/p470/romstage.c<br>M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c<br>M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c<br>M src/mainboard/ibase/mb899/devicetree.cb<br>M src/mainboard/ibase/mb899/romstage.c<br>M src/mainboard/intel/d510mo/romstage.c<br>M src/mainboard/intel/d945gclf/romstage.c<br>M src/mainboard/kontron/986lcd-m/romstage.c<br>M src/mainboard/lenovo/t60/romstage.c<br>M src/mainboard/lenovo/x60/romstage.c<br>M src/mainboard/lenovo/z61t/romstage.c<br>M src/mainboard/roda/rk886ex/romstage.c<br>M src/southbridge/intel/i82801gx/chip.h<br>M src/southbridge/intel/i82801gx/i82801gx.c<br>M src/southbridge/intel/i82801gx/i82801gx.h<br>19 files changed, 99 insertions(+), 81 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/23662/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c</span><br><span>index 79cc35d..3dc62e2 100644</span><br><span>--- a/src/mainboard/apple/macbook21/romstage.c</span><br><span>+++ b/src/mainboard/apple/macbook21/romstage.c</span><br><span>@@ -169,11 +169,6 @@</span><br><span> /* Enable IOAPIC */</span><br><span> RCBA8(OIC) = 0x03;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN</span><br><span style="color: hsl(0, 100%, 40%);">- | FD_ACMOD | FD_ACAUD;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) |= (1 << 0); /* Required. */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Set up I/O Trap #0 for 0xfe00 (SMIC) */</span><br><span> </span><br><span> /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */</span><br><span>diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c</span><br><span>index 4498b10..ff09ce8 100644</span><br><span>--- a/src/mainboard/asrock/g41c-gs/romstage.c</span><br><span>+++ b/src/mainboard/asrock/g41c-gs/romstage.c</span><br><span>@@ -64,8 +64,6 @@</span><br><span> reg32 = RCBA32(GCS);</span><br><span> reg32 |= (1 << 5);</span><br><span> RCBA32(GCS) = reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD</span><br><span style="color: hsl(0, 100%, 40%);">- | FD_ACAUD | 1;</span><br><span> RCBA32(CG) = 0x00000001;</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c</span><br><span>index e1725d0..53d4546 100644</span><br><span>--- a/src/mainboard/asus/p5gc-mx/romstage.c</span><br><span>+++ b/src/mainboard/asus/p5gc-mx/romstage.c</span><br><span>@@ -123,10 +123,6 @@</span><br><span> /* Enable IOAPIC */</span><br><span> RCBA8(OIC) = 0x03;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD</span><br><span style="color: hsl(0, 100%, 40%);">- | FD_ACAUD | 1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Enable PCIe Root Port Clock Gate */</span><br><span> RCBA32(CG) = 0x00000001;</span><br><span> }</span><br><span>diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c</span><br><span>index 5ea41ea..2aded61 100644</span><br><span>--- a/src/mainboard/foxconn/g41s-k/romstage.c</span><br><span>+++ b/src/mainboard/foxconn/g41s-k/romstage.c</span><br><span>@@ -66,8 +66,6 @@</span><br><span> RCBA8(OIC) = 0x03;</span><br><span> RCBA8(OIC);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN |</span><br><span style="color: hsl(0, 100%, 40%);">- FD_ACMOD | FD_ACAUD | FD_PATA | 1;</span><br><span> RCBA32(CG) = 0x00000001;</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c</span><br><span>index e58ef1b..42bc8bc 100644</span><br><span>--- a/src/mainboard/getac/p470/romstage.c</span><br><span>+++ b/src/mainboard/getac/p470/romstage.c</span><br><span>@@ -166,10 +166,6 @@</span><br><span> /* Enable IOAPIC */</span><br><span> RCBA8(OIC) = 0x03;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) |= (1 << 0); // Required.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Enable PCIe Root Port Clock Gate */</span><br><span> // RCBA32(0x341c) = 0x00000001;</span><br><span> </span><br><span>diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c</span><br><span>index 926a5a7..aecac08 100644</span><br><span>--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c</span><br><span>+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c</span><br><span>@@ -86,9 +86,6 @@</span><br><span> /* Enable IOAPIC */</span><br><span> RCBA8(OIC) = 0x03;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = 0x003c0061;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Enable PCIe Root Port Clock Gate */</span><br><span> RCBA32(CG) = 0x00000001;</span><br><span> }</span><br><span>diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c</span><br><span>index ac336e4..fb70134 100644</span><br><span>--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c</span><br><span>+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c</span><br><span>@@ -103,8 +103,6 @@</span><br><span> RCBA8(OIC);</span><br><span> </span><br><span> RCBA32(GCS) = 0x00190464;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD</span><br><span style="color: hsl(0, 100%, 40%);">- | FD_ACAUD | 1;</span><br><span> RCBA32(CG) = 0x00000000;</span><br><span> RCBA32(0x3430) = 0x00000001;</span><br><span> RCBA32(0x3e00) = 0xff000001;</span><br><span>diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb</span><br><span>index c63e5d6..06d25be 100644</span><br><span>--- a/src/mainboard/ibase/mb899/devicetree.cb</span><br><span>+++ b/src/mainboard/ibase/mb899/devicetree.cb</span><br><span>@@ -41,6 +41,8 @@</span><br><span> register "c3_latency" = "85"</span><br><span> register "p_cnt_throttling_supported" = "0"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_port_coalesce" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #device pci 1b.0 on end # High Definition Audio</span><br><span> device pci 1c.0 on end # PCIe</span><br><span> device pci 1c.1 on end # PCIe</span><br><span>diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c</span><br><span>index 0d3b839..dd991d9 100644</span><br><span>--- a/src/mainboard/ibase/mb899/romstage.c</span><br><span>+++ b/src/mainboard/ibase/mb899/romstage.c</span><br><span>@@ -190,7 +190,6 @@</span><br><span> reg32 &= ~(3 << 0);</span><br><span> reg32 |= (1 << 0);</span><br><span> RCBA32(0x3430) = reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) |= (1 << 0);</span><br><span> RCBA16(0x0200) = 0x2008;</span><br><span> RCBA8(0x2027) = 0x0d;</span><br><span> RCBA16(0x3e08) |= (1 << 7);</span><br><span>diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c</span><br><span>index b2044c1..afea7f2 100644</span><br><span>--- a/src/mainboard/intel/d510mo/romstage.c</span><br><span>+++ b/src/mainboard/intel/d510mo/romstage.c</span><br><span>@@ -83,10 +83,6 @@</span><br><span> </span><br><span> /* Enable IOAPIC */</span><br><span> RCBA8(OIC) = 0x03;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD</span><br><span style="color: hsl(0, 100%, 40%);">- | FD_PATA;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) |= 1;</span><br><span> }</span><br><span> </span><br><span> void mainboard_romstage_entry(unsigned long bist)</span><br><span>diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c</span><br><span>index 27c1e3e..b316ed0 100644</span><br><span>--- a/src/mainboard/intel/d945gclf/romstage.c</span><br><span>+++ b/src/mainboard/intel/d945gclf/romstage.c</span><br><span>@@ -66,12 +66,6 @@</span><br><span> /* Enable IOAPIC */</span><br><span> RCBA8(OIC) = 0x03;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices */</span><br><span style="color: hsl(0, 100%, 40%);">- // FIXME devicetree disables pcie3 not 2.</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE2 | (1 << 10) | FD_INTLAN</span><br><span style="color: hsl(0, 100%, 40%);">- | FD_ACMOD | FD_ACAUD;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) |= 1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Enable PCIe Root Port Clock Gate */</span><br><span> // RCBA32(0x341c) = 0x00000001;</span><br><span> }</span><br><span>diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c</span><br><span>index f7e8131..6770b2f 100644</span><br><span>--- a/src/mainboard/kontron/986lcd-m/romstage.c</span><br><span>+++ b/src/mainboard/kontron/986lcd-m/romstage.c</span><br><span>@@ -202,23 +202,7 @@</span><br><span> /* Enable IOAPIC */</span><br><span> RCBA8(OIC) = 0x03;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Now, this is a bit ugly. As per PCI specification, function 0 of a</span><br><span style="color: hsl(0, 100%, 40%);">- * device always has to be implemented. So disabling ethernet port 1</span><br><span style="color: hsl(0, 100%, 40%);">- * would essentially disable all three ethernet ports of the mainboard.</span><br><span style="color: hsl(0, 100%, 40%);">- * It's possible to rename the ports to achieve compatibility to the</span><br><span style="color: hsl(0, 100%, 40%);">- * PCI spec but this will confuse all (static!) tables containing</span><br><span style="color: hsl(0, 100%, 40%);">- * interrupt routing information.</span><br><span style="color: hsl(0, 100%, 40%);">- * To avoid this, we enable (unused) port 6 and swap it with port 1</span><br><span style="color: hsl(0, 100%, 40%);">- * in the case that ethernet port 1 is disabled. Since no devices</span><br><span style="color: hsl(0, 100%, 40%);">- * are connected to that port, we don't have to worry about interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- * routing.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- int port_shuffle = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Disable unused devices */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = FD_ACMOD|FD_ACAUD|FD_PATA;</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> if (read_option(ethernet1, 0) != 0) {</span><br><span> printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n");</span><br><span> reg32 |= FD_PCIE1;</span><br><span>@@ -226,23 +210,10 @@</span><br><span> if (read_option(ethernet2, 0) != 0) {</span><br><span> printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n");</span><br><span> reg32 |= FD_PCIE2;</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg32 & FD_PCIE1)</span><br><span style="color: hsl(0, 100%, 40%);">- port_shuffle = 1;</span><br><span> }</span><br><span> if (read_option(ethernet3, 0) != 0) {</span><br><span> printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n");</span><br><span> reg32 |= FD_PCIE3;</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg32 & FD_PCIE1)</span><br><span style="color: hsl(0, 100%, 40%);">- port_shuffle = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (port_shuffle) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable PCIE6 again */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 &= ~FD_PCIE6;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Swap PCIE6 and PCIE1 */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(RPFN) = 0x00043215;</span><br><span> }</span><br><span> </span><br><span> reg32 |= 1;</span><br><span>diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c</span><br><span>index 18470ea..ee5f4a5 100644</span><br><span>--- a/src/mainboard/lenovo/t60/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/t60/romstage.c</span><br><span>@@ -100,10 +100,6 @@</span><br><span> /* Enable IOAPIC */</span><br><span> RCBA8(OIC) = 0x03;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) |= (1 << 0); // Required.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Set up I/O Trap #0 for 0xfe00 (SMIC) */</span><br><span> RCBA32(0x1e84) = 0x00020001;</span><br><span> RCBA32(0x1e80) = 0x0000fe01;</span><br><span>diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c</span><br><span>index 0eac15a..7050645 100644</span><br><span>--- a/src/mainboard/lenovo/x60/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/x60/romstage.c</span><br><span>@@ -99,10 +99,6 @@</span><br><span> /* Enable IOAPIC */</span><br><span> RCBA8(OIC) = 0x03;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) |= (1 << 0); // Required.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Set up I/O Trap #0 for 0xfe00 (SMIC) */</span><br><span> RCBA32(0x1e84) = 0x00020001;</span><br><span> RCBA32(0x1e80) = 0x0000fe01;</span><br><span>diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c</span><br><span>index ffb72e3..8825d7d 100644</span><br><span>--- a/src/mainboard/lenovo/z61t/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/z61t/romstage.c</span><br><span>@@ -100,10 +100,6 @@</span><br><span> /* Enable IOAPIC */</span><br><span> RCBA8(OIC) = 0x03;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) |= (1 << 0); // Required.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Set up I/O Trap #0 for 0xfe00 (SMIC) */</span><br><span> RCBA32(0x1e84) = 0x00020001;</span><br><span> RCBA32(IOTR0) = 0x0000fe01;</span><br><span>diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c</span><br><span>index b4611f5..0e4adbc 100644</span><br><span>--- a/src/mainboard/roda/rk886ex/romstage.c</span><br><span>+++ b/src/mainboard/roda/rk886ex/romstage.c</span><br><span>@@ -134,11 +134,6 @@</span><br><span> /* Enable IOAPIC */</span><br><span> RCBA8(OIC) = 0x03;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused devices */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 |</span><br><span style="color: hsl(0, 100%, 40%);">- FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(FD) |= (1 << 0); /* Required. */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* This should probably go into the ACPI OS Init trap */</span><br><span> </span><br><span> /* Set up I/O Trap #0 for 0xfe00 (SMIC) */</span><br><span>diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h</span><br><span>index e89fcc4..a21a344 100644</span><br><span>--- a/src/southbridge/intel/i82801gx/chip.h</span><br><span>+++ b/src/southbridge/intel/i82801gx/chip.h</span><br><span>@@ -70,6 +70,10 @@</span><br><span> int docking_supported:1;</span><br><span> int p_cnt_throttling_supported:1;</span><br><span> int c3_latency;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable linear PCIe Root Port function numbers starting at zero */</span><br><span style="color: hsl(120, 100%, 40%);">+ int pcie_port_coalesce;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> };</span><br><span> </span><br><span> #endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */</span><br><span>diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c</span><br><span>index aab674b..b284876 100644</span><br><span>--- a/src/southbridge/intel/i82801gx/i82801gx.c</span><br><span>+++ b/src/southbridge/intel/i82801gx/i82801gx.c</span><br><span>@@ -35,7 +35,98 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static int i82801gx_function_disabled(const unsigned int busn,</span><br><span style="color: hsl(120, 100%, 40%);">+ const unsigned int devfn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct device *const dev = dev_find_slot(busn, devfn);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_EMERG,</span><br><span style="color: hsl(120, 100%, 40%);">+ "PCI device %x:%x.%x"</span><br><span style="color: hsl(120, 100%, 40%);">+ " is not listed in devicetree. Disabling it\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ busn, PCI_SLOT(devfn), PCI_FUNC(devfn));</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return !dev->enabled;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void i82801gx_hide_functions(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FIXME: This works pretty good if the devicetree is consistent. But</span><br><span style="color: hsl(120, 100%, 40%);">+ some functions have to be disabled in right order and/or have</span><br><span style="color: hsl(120, 100%, 40%);">+ other constraints. */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = RCBA32(FD);</span><br><span style="color: hsl(120, 100%, 40%);">+ struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ int devfn;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ } functions[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1b, 0), FD_HDAUD }, /* HD Audio */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1c, 0), FD_PCIE1 }, /* PCIe #1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1c, 1), FD_PCIE2 }, /* PCIe #2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1c, 2), FD_PCIE3 }, /* PCIe #3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1c, 3), FD_PCIE4 }, /* PCIe #4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1c, 4), FD_PCIE5 }, /* PCIe #5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1c, 5), FD_PCIE6 }, /* PCIe #6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1d, 0), FD_UHCI1234 }, /* UHCI #1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1d, 1), FD_UHCI234 }, /* UHCI #2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1d, 2), FD_UHCI34 }, /* UHCI #3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1d, 3), FD_UHCI4 }, /* UHCI #3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1d, 7), FD_EHCI }, /* EHCI #1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1e, 2), FD_ACAUD }, /* AC ’97 Audio */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1e, 3), FD_ACMOD }, /* AC ’97 Modem */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1f, 0), FD_LPCB }, /* LPC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1f, 1), FD_PATA }, /* PATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1f, 2), FD_SATA }, /* SATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ { PCI_DEVFN(0x1f, 3), FD_SMBUS }, /* SMBus */</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < ARRAY_SIZE(functions); ++i) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (i82801gx_function_disabled(0, functions[i].devfn))</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= functions[i].mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (i82801gx_function_disabled(1, PCI_DEVFN(0x08, 0)))</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= FD_INTLAN;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(FD) = reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(FD) |= (1 << 0); /* BIOS must write this... */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void i82801gx_port_coalesing(</span><br><span style="color: hsl(120, 100%, 40%);">+ struct southbridge_intel_i82801gx_config *chip_info)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reg32 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ int next_port = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (RCBA32(FD) & FD_PCIE1)</span><br><span style="color: hsl(120, 100%, 40%);">+ chip_info->pcie_port_coalesce = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!chip_info->pcie_port_coalesce)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < 6; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (i82801gx_function_disabled(0, PCI_DEVFN(0x1c, i)))</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= next_port++ << (i * 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < 6; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (i82801gx_function_disabled(0, PCI_DEVFN(0x1c, i)))</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= next_port++ << (i * 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void i82801gx_init(void *chip_info)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ i82801gx_hide_functions();</span><br><span style="color: hsl(120, 100%, 40%);">+ i82801gx_port_coalesing(chip_info);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct chip_operations southbridge_intel_i82801gx_ops = {</span><br><span> CHIP_NAME("Intel ICH7/ICH7-M (82801Gx) Series Southbridge")</span><br><span> .enable_dev = i82801gx_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+ .init = i82801gx_init,</span><br><span> };</span><br><span>diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h</span><br><span>index df744fc..8f0c10f 100644</span><br><span>--- a/src/southbridge/intel/i82801gx/i82801gx.h</span><br><span>+++ b/src/southbridge/intel/i82801gx/i82801gx.h</span><br><span>@@ -290,8 +290,8 @@</span><br><span> * must know about it, too! */</span><br><span> #define FD_UHCI4 (1 << 11)</span><br><span> #define FD_UHCI34 ((1 << 10) | FD_UHCI4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_UHCI234 ((1 << 9) | FD_UHCI3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FD_UHCI1234 ((1 << 8) | FD_UHCI2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_UHCI234 ((1 << 9) | FD_UHCI34)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FD_UHCI1234 ((1 << 8) | FD_UHCI234)</span><br><span> </span><br><span> #define FD_INTLAN (1 << 7)</span><br><span> #define FD_ACMOD (1 << 6)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23662">change 23662</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23662"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2f6f270c631b97ececf1bd3c23f19b27828e6885 </div>
<div style="display:none"> Gerrit-Change-Number: 23662 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>