[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add basic CPU PM entry of FSP

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/23580


Change subject: soc/intel/cannonlake: Add basic CPU PM entry of FSP
......................................................................

soc/intel/cannonlake: Add basic CPU PM entry of FSP

Enable coreboot's ability of update basic CPU power management about
package power limit 1 and package power limit 2.

BUG=b.72574971
TEST=Build and flash to meowth platform, able to boot up fine into OS.
Update PPL1 in coreboot, and combine with debug build FSP can see
desired value got printed.

Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/chip.h
2 files changed, 14 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/23580/1

diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index f05b55a..e2d4a82 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -180,6 +180,7 @@
 {
 	int i;
 	FSP_S_CONFIG *params = &supd->FspsConfig;
+	FSP_S_TEST_CONFIG *params_t = &supd->FspsTestConfig;
 	const struct device *dev = SA_DEV_ROOT;
 	config_t *config = dev->chip_info;
 
@@ -269,6 +270,11 @@
 	params->Device4Enable = config->Device4Enable;
 	params->SkipMpInit = config->FspSkipMpInit;
 
+	/* Cpu Basic Powermanagement */
+	params_t->PowerLimit1 = config->PPL1Power;
+	params_t->PowerLimit2 = config->PPL2_enable;
+	params_t->PowerLimit2Power = config->PPL2Power;
+
 	/* VrConfig Settings for 5 domains
 	 * 0 = System Agent, 1 = IA Core, 2 = Ring,
 	 * 3 = GT unsliced,  4 = GT sliced */
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index a42494c..64de442 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -85,6 +85,14 @@
 	/* TCC activation offset */
 	uint32_t tcc_offset;
 
+	/* CPU Basic Power Management
+	 * Package PL1 - Package long duration turbo mode power limit
+	 * Package PL2 - Short Duration Turbo Mode
+	 * Package PL1 - Package short duration turbo mode power limit */
+	uint32_t PPL1Power;
+	uint32_t PPL2_enable;
+	uint32_t PPL2Power;
+
 	uint64_t PlatformMemorySize;
 	uint8_t SmramMask;
 	uint8_t MrcFastBoot;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047
Gerrit-Change-Number: 23580
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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