<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23580">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add basic CPU PM entry of FSP<br><br>Enable coreboot's ability of update basic CPU power management about<br>package power limit 1 and package power limit 2.<br><br>BUG=b.72574971<br>TEST=Build and flash to meowth platform, able to boot up fine into OS.<br>Update PPL1 in coreboot, and combine with debug build FSP can see<br>desired value got printed.<br><br>Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/chip.c<br>M src/soc/intel/cannonlake/chip.h<br>2 files changed, 14 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/23580/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c</span><br><span>index f05b55a..e2d4a82 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip.c</span><br><span>@@ -180,6 +180,7 @@</span><br><span> {</span><br><span>   int i;</span><br><span>       FSP_S_CONFIG *params = &supd->FspsConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+      FSP_S_TEST_CONFIG *params_t = &supd->FspsTestConfig;</span><br><span>  const struct device *dev = SA_DEV_ROOT;</span><br><span>      config_t *config = dev->chip_info;</span><br><span> </span><br><span>@@ -269,6 +270,11 @@</span><br><span>     params->Device4Enable = config->Device4Enable;</span><br><span>         params->SkipMpInit = config->FspSkipMpInit;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* Cpu Basic Powermanagement */</span><br><span style="color: hsl(120, 100%, 40%);">+       params_t->PowerLimit1 = config->PPL1Power;</span><br><span style="color: hsl(120, 100%, 40%);">+      params_t->PowerLimit2 = config->PPL2_enable;</span><br><span style="color: hsl(120, 100%, 40%);">+    params_t->PowerLimit2Power = config->PPL2Power;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>      /* VrConfig Settings for 5 domains</span><br><span>    * 0 = System Agent, 1 = IA Core, 2 = Ring,</span><br><span>   * 3 = GT unsliced,  4 = GT sliced */</span><br><span>diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h</span><br><span>index a42494c..64de442 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.h</span><br><span>+++ b/src/soc/intel/cannonlake/chip.h</span><br><span>@@ -85,6 +85,14 @@</span><br><span>  /* TCC activation offset */</span><br><span>  uint32_t tcc_offset;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+      /* CPU Basic Power Management</span><br><span style="color: hsl(120, 100%, 40%);">+  * Package PL1 - Package long duration turbo mode power limit</span><br><span style="color: hsl(120, 100%, 40%);">+  * Package PL2 - Short Duration Turbo Mode</span><br><span style="color: hsl(120, 100%, 40%);">+     * Package PL1 - Package short duration turbo mode power limit */</span><br><span style="color: hsl(120, 100%, 40%);">+     uint32_t PPL1Power;</span><br><span style="color: hsl(120, 100%, 40%);">+   uint32_t PPL2_enable;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t PPL2Power;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>        uint64_t PlatformMemorySize;</span><br><span>         uint8_t SmramMask;</span><br><span>   uint8_t MrcFastBoot;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23580">change 23580</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23580"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047 </div>
<div style="display:none"> Gerrit-Change-Number: 23580 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>