[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Clear RTC failure bit after reading it

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/23578


Change subject: soc/intel/apollolake: Clear RTC failure bit after reading it
......................................................................

soc/intel/apollolake: Clear RTC failure bit after reading it

This change ensures that the RTC failure bit is cleared in PMCON1
after cmos_init checks for it. Before this change, RPS was cleared
in dev init phase. If any reboot occurred before dev init stage
(e.g. FSP reset) then RPS won't be cleared and cmos_init will
re-initialize CMOS data. This resulted in any information like VBNV
flags stored in CMOS after first cmos_init to be lost.

BUG=b:72879807
BRANCH=coral
TEST=Verified that recovery request is preserved when recovery is
requested without battery on coral.

Change-Id: Ib23b1fcd5c3624bad6ab83dce17a469b2f5b5ba8
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/apollolake/include/soc/pm.h
M src/soc/intel/apollolake/pmutil.c
2 files changed, 21 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/23578/1

diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 34b9f96..0ab53af 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -173,8 +173,13 @@
 #define  COLD_BOOT_STS		(1 << 27)
 #define  COLD_RESET_STS		(1 << 26)
 #define  WARM_RESET_STS		(1 << 25)
+#define  GLOBAL_RESET_STS	(1 << 24)
 #define  SRS			(1 << 20)
+#define  MS4V			(1 << 18)
 #define  RPS			(1 << 2)
+#define GEN_PMCON1_CLR1_BITS	(COLD_BOOT_STS | COLD_RESET_STS | \
+				 WARM_RESET_STS | GLOBAL_RESET_STS |\
+				 SRS | MS4V)
 #define GEN_PMCON2		0x1024
 #define GEN_PMCON3		0x1028
 #       define SLP_S3_ASSERT_WIDTH_SHIFT	10
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index dbaed70..2900e6d 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -232,5 +232,20 @@
 
 int vbnv_cmos_failed(void)
 {
-	return rtc_failed(read32((void *)(read_pmc_mmio_bar() + GEN_PMCON1)));
+	uintptr_t pmc_bar = read_pmc_mmio_bar();
+	uint32_t gen_pmcon1 = read32((void *)(pmc_bar + GEN_PMCON1));
+	int rtc_failure = rtc_failed(gen_pmcon1);
+
+	/* We do not want to write 1 to clear-1 bits. So set them to 0. */
+	gen_pmcon &= ~GEN_PMCON1_CLR1_BITS;
+
+	/* RPS is write 0 to clear. */
+	gen_pmcon &= ~RPS;
+
+	if (rtc_failure) {
+		printk(BIOS_INFO, "RTC failed!\n");
+		write32((void *)(pmc_bar + GEN_PMCON1), gen_pmcon1);
+	}
+
+	return rtc_failure;
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib23b1fcd5c3624bad6ab83dce17a469b2f5b5ba8
Gerrit-Change-Number: 23578
Gerrit-PatchSet: 1
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
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