<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23578">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Clear RTC failure bit after reading it<br><br>This change ensures that the RTC failure bit is cleared in PMCON1<br>after cmos_init checks for it. Before this change, RPS was cleared<br>in dev init phase. If any reboot occurred before dev init stage<br>(e.g. FSP reset) then RPS won't be cleared and cmos_init will<br>re-initialize CMOS data. This resulted in any information like VBNV<br>flags stored in CMOS after first cmos_init to be lost.<br><br>BUG=b:72879807<br>BRANCH=coral<br>TEST=Verified that recovery request is preserved when recovery is<br>requested without battery on coral.<br><br>Change-Id: Ib23b1fcd5c3624bad6ab83dce17a469b2f5b5ba8<br>Signed-off-by: Furquan Shaikh <furquan@chromium.org><br>---<br>M src/soc/intel/apollolake/include/soc/pm.h<br>M src/soc/intel/apollolake/pmutil.c<br>2 files changed, 21 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/23578/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h</span><br><span>index 34b9f96..0ab53af 100644</span><br><span>--- a/src/soc/intel/apollolake/include/soc/pm.h</span><br><span>+++ b/src/soc/intel/apollolake/include/soc/pm.h</span><br><span>@@ -173,8 +173,13 @@</span><br><span> #define COLD_BOOT_STS (1 << 27)</span><br><span> #define COLD_RESET_STS (1 << 26)</span><br><span> #define WARM_RESET_STS (1 << 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GLOBAL_RESET_STS (1 << 24)</span><br><span> #define SRS (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MS4V (1 << 18)</span><br><span> #define RPS (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEN_PMCON1_CLR1_BITS (COLD_BOOT_STS | COLD_RESET_STS | \</span><br><span style="color: hsl(120, 100%, 40%);">+ WARM_RESET_STS | GLOBAL_RESET_STS |\</span><br><span style="color: hsl(120, 100%, 40%);">+ SRS | MS4V)</span><br><span> #define GEN_PMCON2 0x1024</span><br><span> #define GEN_PMCON3 0x1028</span><br><span> # define SLP_S3_ASSERT_WIDTH_SHIFT 10</span><br><span>diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c</span><br><span>index dbaed70..2900e6d 100644</span><br><span>--- a/src/soc/intel/apollolake/pmutil.c</span><br><span>+++ b/src/soc/intel/apollolake/pmutil.c</span><br><span>@@ -232,5 +232,20 @@</span><br><span> </span><br><span> int vbnv_cmos_failed(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- return rtc_failed(read32((void *)(read_pmc_mmio_bar() + GEN_PMCON1)));</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t pmc_bar = read_pmc_mmio_bar();</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gen_pmcon1 = read32((void *)(pmc_bar + GEN_PMCON1));</span><br><span style="color: hsl(120, 100%, 40%);">+ int rtc_failure = rtc_failed(gen_pmcon1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We do not want to write 1 to clear-1 bits. So set them to 0. */</span><br><span style="color: hsl(120, 100%, 40%);">+ gen_pmcon &= ~GEN_PMCON1_CLR1_BITS;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* RPS is write 0 to clear. */</span><br><span style="color: hsl(120, 100%, 40%);">+ gen_pmcon &= ~RPS;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (rtc_failure) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "RTC failed!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((void *)(pmc_bar + GEN_PMCON1), gen_pmcon1);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return rtc_failure;</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23578">change 23578</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23578"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib23b1fcd5c3624bad6ab83dce17a469b2f5b5ba8 </div>
<div style="display:none"> Gerrit-Change-Number: 23578 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>