[coreboot-gerrit] Change in coreboot[master]: sb/broadcom/bcm5785/early_setup.c: Fix coding style

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23577


Change subject: sb/broadcom/bcm5785/early_setup.c: Fix coding style
......................................................................

sb/broadcom/bcm5785/early_setup.c: Fix coding style

Change-Id: Ic8218078f4b1075b41f769e26e34adf9c9b113ac
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/southbridge/broadcom/bcm5785/early_setup.c
1 file changed, 22 insertions(+), 22 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/23577/1

diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c
index 7235444..2c79239 100644
--- a/src/southbridge/broadcom/bcm5785/early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/early_setup.c
@@ -27,13 +27,13 @@
 	/* LPC Control 0 */
 	byte = pci_read_config8(dev, 0x44);
 	/* Serial 0 */
-	byte |= (1<<6);
+	byte |= (1 << 6);
 	pci_write_config8(dev, 0x44, byte);
 
 	/* LPC Control 4 */
 	byte = pci_read_config8(dev, 0x48);
 	/* superio port 0x2e/4e enable */
-	byte |=(1<<1)|(1<<0);
+	byte |= (1 << 1)|(1 << 0);
 	pci_write_config8(dev, 0x48, byte);
 }
 
@@ -46,21 +46,19 @@
 	dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
 
 	dword_old = pci_read_config32(dev, 0x4c);
-	dword = dword_old | (1<<4); //enable Timer Func
-	if (dword != dword_old ) {
+	dword = dword_old | (1 << 4); //enable Timer Func
+	if (dword != dword_old)
 		pci_write_config32(dev, 0x4c, dword);
-	}
 
 	dword_old = pci_read_config32(dev, 0x6c);
-	dword = dword_old | (1<<9); //unhide Timer Func in pci space
-	if (dword != dword_old ) {
+	dword = dword_old | (1 << 9); //unhide Timer Func in pci space
+	if (dword != dword_old)
 		pci_write_config32(dev, 0x6c, dword);
-	}
 
 	dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);
 
 	/* enable cf9 */
-	pci_write_config8(dev, 0x40, (1<<2));
+	pci_write_config8(dev, 0x40, (1 << 2));
 }
 
 unsigned get_sbdn(unsigned bus)
@@ -74,7 +72,7 @@
 		PCI_ID(0x1166, 0x0036),
 		bus);
 
-	return (dev>>15) & 0x1f;
+	return (dev >> 15) & 0x1f;
 
 }
 
@@ -84,7 +82,7 @@
 {
 	//ACPI Decode Enable
 	outb(0x0e, 0xcd6);
-	outb((1<<3), 0xcd7);
+	outb((1 << 3), 0xcd7);
 
 	// set port to 0x2060
 	outb(0x67, 0xcd6);
@@ -138,7 +136,7 @@
 	dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
 
 	byte = pci_read_config8(dev, 0x42);
-	byte = (1<<1); //enable a20
+	byte = (1 << 1); //enable a20
 	pci_write_config8(dev, 0x42, byte);
 
 	dword_old = pci_read_config32(dev, 0x6c);
@@ -148,10 +146,12 @@
 	// bit 2: enable keyboard init message
 	// bit 1: enable upsteam messages
 	// bit 0: enable shutdowm message to init generation
-	dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor
-	if (dword != dword_old ) {
+
+	/* bit 1 and bit 4 must be set, otherwise
+	 * interrupt msg will not be delivered to the processor */
+	dword = dword_old|(1 << 5)|(1 << 3)|(1 << 2)|(1 << 1)|(1 << 0);
+	if (dword != dword_old)
 		pci_write_config32(dev, 0x6c, dword);
-	}
 }
 
 static void bcm5785_early_setup(void)
@@ -164,13 +164,13 @@
 	// enable device on bcm5785 at first
 	dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
 	dword = pci_read_config32(dev, 0x64);
-	dword |=  (1<<15) | (1<<11) | (1<<3); // ioapci enable
-	dword |= (1<<8); // USB enable
-	dword |= /* (1<<27)|*/(1<<14); // IDE enable
+	dword |=  (1 << 15) | (1 << 11) | (1 << 3); // ioapci enable
+	dword |= (1 << 8); // USB enable
+	dword |= /* (1 << 27)|*/(1 << 14); // IDE enable
 	pci_write_config32(dev, 0x64, dword);
 
 	byte = pci_read_config8(dev, 0x84);
-	byte |= (1<<0); // SATA enable
+	byte |= (1 << 0); // SATA enable
 	pci_write_config8(dev, 0x84, byte);
 
 // WDT and cf9 for later in ramstage to call hard_reset
@@ -182,7 +182,7 @@
 // IDE related
 	//F0
 	byte = pci_read_config8(dev, 0x4e);
-	byte |= (1<<4); //enable IDE ext regs
+	byte |= (1 << 4); //enable IDE ext regs
 	pci_write_config8(dev, 0x4e, byte);
 
 	//F1
@@ -193,7 +193,7 @@
 	pci_write_config8(dev, 0xb0, 0x01);
 	pci_write_config8(dev, 0xb2, 0x02);
 	byte = pci_read_config8(dev, 0x06);
-	byte |= (1<<4); // so b0, b2 can not be changed from now
+	byte |= (1 << 4); // so b0, b2 can not be changed from now
 	pci_write_config8(dev, 0x06, byte);
 	byte = pci_read_config8(dev, 0x49);
 	byte |= 1; // enable second channel
@@ -203,7 +203,7 @@
 	dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
 
 	byte = pci_read_config8(dev, 0x40);
-	byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable
+	byte |= (1 << 3)|(1 << 2); // LPC Retry, LPC to PCI DMA enable
 	pci_write_config8(dev, 0x40, byte);
 
 	pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic8218078f4b1075b41f769e26e34adf9c9b113ac
Gerrit-Change-Number: 23577
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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