<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23577">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/broadcom/bcm5785/early_setup.c: Fix coding style<br><br>Change-Id: Ic8218078f4b1075b41f769e26e34adf9c9b113ac<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/broadcom/bcm5785/early_setup.c<br>1 file changed, 22 insertions(+), 22 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/23577/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c</span><br><span>index 7235444..2c79239 100644</span><br><span>--- a/src/southbridge/broadcom/bcm5785/early_setup.c</span><br><span>+++ b/src/southbridge/broadcom/bcm5785/early_setup.c</span><br><span>@@ -27,13 +27,13 @@</span><br><span> /* LPC Control 0 */</span><br><span> byte = pci_read_config8(dev, 0x44);</span><br><span> /* Serial 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- byte |= (1<<6);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte |= (1 << 6);</span><br><span> pci_write_config8(dev, 0x44, byte);</span><br><span> </span><br><span> /* LPC Control 4 */</span><br><span> byte = pci_read_config8(dev, 0x48);</span><br><span> /* superio port 0x2e/4e enable */</span><br><span style="color: hsl(0, 100%, 40%);">- byte |=(1<<1)|(1<<0);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte |= (1 << 1)|(1 << 0);</span><br><span> pci_write_config8(dev, 0x48, byte);</span><br><span> }</span><br><span> </span><br><span>@@ -46,21 +46,19 @@</span><br><span> dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);</span><br><span> </span><br><span> dword_old = pci_read_config32(dev, 0x4c);</span><br><span style="color: hsl(0, 100%, 40%);">- dword = dword_old | (1<<4); //enable Timer Func</span><br><span style="color: hsl(0, 100%, 40%);">- if (dword != dword_old ) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dword = dword_old | (1 << 4); //enable Timer Func</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dword != dword_old)</span><br><span> pci_write_config32(dev, 0x4c, dword);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span> </span><br><span> dword_old = pci_read_config32(dev, 0x6c);</span><br><span style="color: hsl(0, 100%, 40%);">- dword = dword_old | (1<<9); //unhide Timer Func in pci space</span><br><span style="color: hsl(0, 100%, 40%);">- if (dword != dword_old ) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dword = dword_old | (1 << 9); //unhide Timer Func in pci space</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dword != dword_old)</span><br><span> pci_write_config32(dev, 0x6c, dword);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span> </span><br><span> dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);</span><br><span> </span><br><span> /* enable cf9 */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, 0x40, (1<<2));</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(dev, 0x40, (1 << 2));</span><br><span> }</span><br><span> </span><br><span> unsigned get_sbdn(unsigned bus)</span><br><span>@@ -74,7 +72,7 @@</span><br><span> PCI_ID(0x1166, 0x0036),</span><br><span> bus);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- return (dev>>15) & 0x1f;</span><br><span style="color: hsl(120, 100%, 40%);">+ return (dev >> 15) & 0x1f;</span><br><span> </span><br><span> }</span><br><span> </span><br><span>@@ -84,7 +82,7 @@</span><br><span> {</span><br><span> //ACPI Decode Enable</span><br><span> outb(0x0e, 0xcd6);</span><br><span style="color: hsl(0, 100%, 40%);">- outb((1<<3), 0xcd7);</span><br><span style="color: hsl(120, 100%, 40%);">+ outb((1 << 3), 0xcd7);</span><br><span> </span><br><span> // set port to 0x2060</span><br><span> outb(0x67, 0xcd6);</span><br><span>@@ -138,7 +136,7 @@</span><br><span> dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);</span><br><span> </span><br><span> byte = pci_read_config8(dev, 0x42);</span><br><span style="color: hsl(0, 100%, 40%);">- byte = (1<<1); //enable a20</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = (1 << 1); //enable a20</span><br><span> pci_write_config8(dev, 0x42, byte);</span><br><span> </span><br><span> dword_old = pci_read_config32(dev, 0x6c);</span><br><span>@@ -148,10 +146,12 @@</span><br><span> // bit 2: enable keyboard init message</span><br><span> // bit 1: enable upsteam messages</span><br><span> // bit 0: enable shutdowm message to init generation</span><br><span style="color: hsl(0, 100%, 40%);">- dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor</span><br><span style="color: hsl(0, 100%, 40%);">- if (dword != dword_old ) {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* bit 1 and bit 4 must be set, otherwise</span><br><span style="color: hsl(120, 100%, 40%);">+ * interrupt msg will not be delivered to the processor */</span><br><span style="color: hsl(120, 100%, 40%);">+ dword = dword_old|(1 << 5)|(1 << 3)|(1 << 2)|(1 << 1)|(1 << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dword != dword_old)</span><br><span> pci_write_config32(dev, 0x6c, dword);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span> }</span><br><span> </span><br><span> static void bcm5785_early_setup(void)</span><br><span>@@ -164,13 +164,13 @@</span><br><span> // enable device on bcm5785 at first</span><br><span> dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);</span><br><span> dword = pci_read_config32(dev, 0x64);</span><br><span style="color: hsl(0, 100%, 40%);">- dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable</span><br><span style="color: hsl(0, 100%, 40%);">- dword |= (1<<8); // USB enable</span><br><span style="color: hsl(0, 100%, 40%);">- dword |= /* (1<<27)|*/(1<<14); // IDE enable</span><br><span style="color: hsl(120, 100%, 40%);">+ dword |= (1 << 15) | (1 << 11) | (1 << 3); // ioapci enable</span><br><span style="color: hsl(120, 100%, 40%);">+ dword |= (1 << 8); // USB enable</span><br><span style="color: hsl(120, 100%, 40%);">+ dword |= /* (1 << 27)|*/(1 << 14); // IDE enable</span><br><span> pci_write_config32(dev, 0x64, dword);</span><br><span> </span><br><span> byte = pci_read_config8(dev, 0x84);</span><br><span style="color: hsl(0, 100%, 40%);">- byte |= (1<<0); // SATA enable</span><br><span style="color: hsl(120, 100%, 40%);">+ byte |= (1 << 0); // SATA enable</span><br><span> pci_write_config8(dev, 0x84, byte);</span><br><span> </span><br><span> // WDT and cf9 for later in ramstage to call hard_reset</span><br><span>@@ -182,7 +182,7 @@</span><br><span> // IDE related</span><br><span> //F0</span><br><span> byte = pci_read_config8(dev, 0x4e);</span><br><span style="color: hsl(0, 100%, 40%);">- byte |= (1<<4); //enable IDE ext regs</span><br><span style="color: hsl(120, 100%, 40%);">+ byte |= (1 << 4); //enable IDE ext regs</span><br><span> pci_write_config8(dev, 0x4e, byte);</span><br><span> </span><br><span> //F1</span><br><span>@@ -193,7 +193,7 @@</span><br><span> pci_write_config8(dev, 0xb0, 0x01);</span><br><span> pci_write_config8(dev, 0xb2, 0x02);</span><br><span> byte = pci_read_config8(dev, 0x06);</span><br><span style="color: hsl(0, 100%, 40%);">- byte |= (1<<4); // so b0, b2 can not be changed from now</span><br><span style="color: hsl(120, 100%, 40%);">+ byte |= (1 << 4); // so b0, b2 can not be changed from now</span><br><span> pci_write_config8(dev, 0x06, byte);</span><br><span> byte = pci_read_config8(dev, 0x49);</span><br><span> byte |= 1; // enable second channel</span><br><span>@@ -203,7 +203,7 @@</span><br><span> dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);</span><br><span> </span><br><span> byte = pci_read_config8(dev, 0x40);</span><br><span style="color: hsl(0, 100%, 40%);">- byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable</span><br><span style="color: hsl(120, 100%, 40%);">+ byte |= (1 << 3)|(1 << 2); // LPC Retry, LPC to PCI DMA enable</span><br><span> pci_write_config8(dev, 0x40, byte);</span><br><span> </span><br><span> pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23577">change 23577</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic8218078f4b1075b41f769e26e34adf9c9b113ac </div>
<div style="display:none"> Gerrit-Change-Number: 23577 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>