[coreboot-gerrit] Change in coreboot[master]: mainboard/gigabyte/m57sli: Fix coding style

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23530


Change subject: mainboard/gigabyte/m57sli: Fix coding style
......................................................................

mainboard/gigabyte/m57sli: Fix coding style

Change-Id: If469989a33b7aaca55503108601fb158f264fc06
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/mainboard/gigabyte/m57sli/mptable.c
1 file changed, 20 insertions(+), 18 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/23530/1

diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
index 019a7f5..e0af483 100644
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ b/src/mainboard/gigabyte/m57sli/mptable.c
@@ -49,7 +49,7 @@
 		device_t dev;
 		struct resource *res;
 
-		dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
+		dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x1, 0));
 		if (dev) {
 			res = find_resource(dev, PCI_BASE_ADDRESS_1);
 			if (res) {
@@ -72,22 +72,23 @@
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\
 			 bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin))
 
-	PCI_INT(0,sbdn+1,1, 10); /* SMBus */
-	PCI_INT(0,sbdn+2,0, 22); /* USB */
-	PCI_INT(0,sbdn+2,1, 23); /* USB */
-	PCI_INT(0,sbdn+4,0, 21); /* IDE */
-	PCI_INT(0,sbdn+5,0, 20); /* SATA */
-	PCI_INT(0,sbdn+5,1, 21); /* SATA */
-	PCI_INT(0,sbdn+5,2, 22); /* SATA */
-	PCI_INT(0,sbdn+6,1, 23); /* HD Audio */
-	PCI_INT(0,sbdn+8,0, 20); /* GBit Ethernet */
+	PCI_INT(0, sbdn + 1, 1, 10); /* SMBus */
+	PCI_INT(0, sbdn + 2, 0, 22); /* USB */
+	PCI_INT(0, sbdn + 2, 1, 23); /* USB */
+	PCI_INT(0, sbdn + 4, 0, 21); /* IDE */
+	PCI_INT(0, sbdn + 5, 0, 20); /* SATA */
+	PCI_INT(0, sbdn + 5, 1, 21); /* SATA */
+	PCI_INT(0, sbdn + 5, 2, 22); /* SATA */
+	PCI_INT(0, sbdn + 6, 1, 23); /* HD Audio */
+	PCI_INT(0, sbdn + 8, 0, 20); /* GBit Ethernet */
 
 	/* The PCIe slots, each on its own bus */
 	k = 1;
-	for(i = 0; i < 4; i++){
-		for(j = 7; j > 1; j--){
-			if(k > 3) k = 0;
-			PCI_INT(j,0,i, 16+k);
+	for (i = 0; i < 4; i++) {
+		for (j = 7; j > 1; j--) {
+			if (k > 3)
+				k = 0;
+			PCI_INT(j, 0, i, 16 + k);
 			k++;
 		}
 		k--;
@@ -98,10 +99,11 @@
 	 * FireWire is j = 10
 	*/
 	k = 2;
-	for(i = 0; i < 4; i++){
-		for(j = 6; j < 11; j++){
-			if(k > 3) k = 0;
-			PCI_INT(1,j,i, 16+k);
+	for (i = 0; i < 4; i++) {
+		for (j = 6; j < 11; j++) {
+			if (k > 3)
+				k = 0;
+			PCI_INT(1, j, i, 16 + k);
 			k++;
 		}
 	}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If469989a33b7aaca55503108601fb158f264fc06
Gerrit-Change-Number: 23530
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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