[coreboot-gerrit] Change in ...coreboot[master]: nb/intel/haswell: Add support for PCIe graphics

[Tristan Corrick (Code Review)]

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30272 )

Change subject: nb/intel/haswell: Add support for PCIe graphics
......................................................................


Patch Set 7: Code-Review-1

(1 comment)

https://review.coreboot.org/#/c/30272/7/src/northbridge/intel/haswell/early_init.c 
File src/northbridge/intel/haswell/early_init.c:

https://review.coreboot.org/#/c/30272/7/src/northbridge/intel/haswell/early_init.c@144 
PS7, Line 144: 	 * It could be possible that the link training is not complete
             : 	 * by the time the MRC makes its decision about disabling VGA IO
             : 	 * decoding on the IGD. However, this has not been observed.
Looks like this happens on S3 resume. When the PEG was doing VGA IO
decode, it causes the MRC to hang...



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I786ecb6eccad8de89778af7e736ed664323e220e
Gerrit-Change-Number: 30272
Gerrit-PatchSet: 7
Gerrit-Owner: Tristan Corrick <tristan at corrick.kiwi>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: Tristan Corrick <tristan at corrick.kiwi>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-CC: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Comment-Date: Mon, 24 Dec 2018 06:38:09 +0000
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