[coreboot-gerrit] Change in ...coreboot[master]: mb/google/hatch: Modify Comatlake flash layout

[V Sowmya (Code Review)]

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30413


Change subject: mb/google/hatch: Modify Comatlake flash layout
......................................................................

mb/google/hatch: Modify Comatlake flash layout

This patch modifies the CML flash layout to support
IFWI 1.6 with the following regions,
Flash Region 0: Descriptor
		[0x0 - 0xFFF]
Flash Region 1: IFWI (consist of ME and PMC FW)
		[0x1000 - 0x3FFFFF]
Flash Region 2: BIOS
		[0x1400000 - 0x1FFFFFF]

Change-Id: I3d05fb50e970737a2552b85d6aebed943bf2b6cb
Signed-off-by: V Sowmya <v.sowmya at intel.com>
---
M src/mainboard/google/hatch/chromeos.fmd
1 file changed, 12 insertions(+), 12 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/30413/1

diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd
index 066cfbf..53ba338 100644
--- a/src/mainboard/google/hatch/chromeos.fmd
+++ b/src/mainboard/google/hatch/chromeos.fmd
@@ -1,20 +1,20 @@
 FLASH at 0xfe000000 0x2000000 {
-	SI_ALL at 0x0 0x300000 {
+	SI_ALL at 0x0 0x400000 {
 		SI_DESC at 0x0 0x1000
-		SI_ME at 0x1000 0x2ff000
+		SI_ME at 0x1000 0x3ff000
 	}
-	SI_BIOS at 0x1000000 0x1000000 {
-		RW_SECTION_A at 0x0 0x300000 {
+	SI_BIOS at 0x1400000 0xC00000 {
+		RW_SECTION_A at 0x0 0x2d0000 {
 			VBLOCK_A at 0x0 0x10000
-			FW_MAIN_A(CBFS)@0x10000 0x2effc0
-			RW_FWID_A at 0x2fffc0 0x40
+			FW_MAIN_A(CBFS)@0x10000 0x2bffc0
+			RW_FWID_A at 0x2cffc0 0x40
 		}
-		RW_SECTION_B at 0x300000 0x300000 {
+		RW_SECTION_B at 0x2d0000 0x2d0000 {
 			VBLOCK_B at 0x0 0x10000
-			FW_MAIN_B(CBFS)@0x10000 0x2effc0
-			RW_FWID_B at 0x2fffc0 0x40
+			FW_MAIN_B(CBFS)@0x10000 0x2bffc0
+			RW_FWID_B at 0x2cffc0 0x40
 		}
-		RW_MISC at 0x600000 0x30000 {
+		RW_MISC at 0x5a0000 0x30000 {
 			UNIFIED_MRC_CACHE at 0x0 0x20000 {
 				RECOVERY_MRC_CACHE at 0x0 0x10000
 				RW_MRC_CACHE at 0x10000 0x10000
@@ -27,8 +27,8 @@
 			RW_VPD at 0x28000 0x2000
 			RW_NVRAM at 0x2a000 0x6000
 		}
-		RW_LEGACY(CBFS)@0x630000 0x5a0000
-		WP_RO at 0xbd0000 0x430000 {
+		RW_LEGACY(CBFS)@0x5d0000 0x200000
+		WP_RO at 0x7d0000 0x430000 {
 			RO_VPD at 0x0 0x4000
 			RO_SECTION at 0x4000 0x42c000 {
 				FMAP at 0x0 0x800

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3d05fb50e970737a2552b85d6aebed943bf2b6cb
Gerrit-Change-Number: 30413
Gerrit-PatchSet: 1
Gerrit-Owner: V Sowmya <v.sowmya at intel.com>
Gerrit-MessageType: newchange
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