<p>V Sowmya has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30413">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/hatch: Modify Comatlake flash layout<br><br>This patch modifies the CML flash layout to support<br>IFWI 1.6 with the following regions,<br>Flash Region 0: Descriptor<br>           [0x0 - 0xFFF]<br>Flash Region 1: IFWI (consist of ME and PMC FW)<br>                [0x1000 - 0x3FFFFF]<br>Flash Region 2: BIOS<br>             [0x1400000 - 0x1FFFFFF]<br><br>Change-Id: I3d05fb50e970737a2552b85d6aebed943bf2b6cb<br>Signed-off-by: V Sowmya <v.sowmya@intel.com><br>---<br>M src/mainboard/google/hatch/chromeos.fmd<br>1 file changed, 12 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/30413/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd</span><br><span>index 066cfbf..53ba338 100644</span><br><span>--- a/src/mainboard/google/hatch/chromeos.fmd</span><br><span>+++ b/src/mainboard/google/hatch/chromeos.fmd</span><br><span>@@ -1,20 +1,20 @@</span><br><span> FLASH@0xfe000000 0x2000000 {</span><br><span style="color: hsl(0, 100%, 40%);">-   SI_ALL@0x0 0x300000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_ALL@0x0 0x400000 {</span><br><span>                SI_DESC@0x0 0x1000</span><br><span style="color: hsl(0, 100%, 40%);">-              SI_ME@0x1000 0x2ff000</span><br><span style="color: hsl(120, 100%, 40%);">+         SI_ME@0x1000 0x3ff000</span><br><span>        }</span><br><span style="color: hsl(0, 100%, 40%);">-       SI_BIOS@0x1000000 0x1000000 {</span><br><span style="color: hsl(0, 100%, 40%);">-           RW_SECTION_A@0x0 0x300000 {</span><br><span style="color: hsl(120, 100%, 40%);">+   SI_BIOS@0x1400000 0xC00000 {</span><br><span style="color: hsl(120, 100%, 40%);">+          RW_SECTION_A@0x0 0x2d0000 {</span><br><span>                  VBLOCK_A@0x0 0x10000</span><br><span style="color: hsl(0, 100%, 40%);">-                    FW_MAIN_A(CBFS)@0x10000 0x2effc0</span><br><span style="color: hsl(0, 100%, 40%);">-                        RW_FWID_A@0x2fffc0 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+                       FW_MAIN_A(CBFS)@0x10000 0x2bffc0</span><br><span style="color: hsl(120, 100%, 40%);">+                      RW_FWID_A@0x2cffc0 0x40</span><br><span>              }</span><br><span style="color: hsl(0, 100%, 40%);">-               RW_SECTION_B@0x300000 0x300000 {</span><br><span style="color: hsl(120, 100%, 40%);">+              RW_SECTION_B@0x2d0000 0x2d0000 {</span><br><span>                     VBLOCK_B@0x0 0x10000</span><br><span style="color: hsl(0, 100%, 40%);">-                    FW_MAIN_B(CBFS)@0x10000 0x2effc0</span><br><span style="color: hsl(0, 100%, 40%);">-                        RW_FWID_B@0x2fffc0 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+                       FW_MAIN_B(CBFS)@0x10000 0x2bffc0</span><br><span style="color: hsl(120, 100%, 40%);">+                      RW_FWID_B@0x2cffc0 0x40</span><br><span>              }</span><br><span style="color: hsl(0, 100%, 40%);">-               RW_MISC@0x600000 0x30000 {</span><br><span style="color: hsl(120, 100%, 40%);">+            RW_MISC@0x5a0000 0x30000 {</span><br><span>                   UNIFIED_MRC_CACHE@0x0 0x20000 {</span><br><span>                              RECOVERY_MRC_CACHE@0x0 0x10000</span><br><span>                               RW_MRC_CACHE@0x10000 0x10000</span><br><span>@@ -27,8 +27,8 @@</span><br><span>                     RW_VPD@0x28000 0x2000</span><br><span>                        RW_NVRAM@0x2a000 0x6000</span><br><span>              }</span><br><span style="color: hsl(0, 100%, 40%);">-               RW_LEGACY(CBFS)@0x630000 0x5a0000</span><br><span style="color: hsl(0, 100%, 40%);">-               WP_RO@0xbd0000 0x430000 {</span><br><span style="color: hsl(120, 100%, 40%);">+             RW_LEGACY(CBFS)@0x5d0000 0x200000</span><br><span style="color: hsl(120, 100%, 40%);">+             WP_RO@0x7d0000 0x430000 {</span><br><span>                    RO_VPD@0x0 0x4000</span><br><span>                    RO_SECTION@0x4000 0x42c000 {</span><br><span>                                 FMAP@0x0 0x800</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30413">change 30413</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30413"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I3d05fb50e970737a2552b85d6aebed943bf2b6cb </div>
<div style="display:none"> Gerrit-Change-Number: 30413 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: V Sowmya <v.sowmya@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>