[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/broadwell: Enable LPC/SIO setup in bootblock
Arthur Heymans (Code Review)
gerrit at coreboot.org
Sat Dec 22 17:04:14 CET 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30385
Change subject: soc/intel/broadwell: Enable LPC/SIO setup in bootblock
......................................................................
soc/intel/broadwell: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock.
Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/google/jecht/Makefile.inc
A src/mainboard/google/jecht/bootblock.c
M src/mainboard/google/jecht/romstage.c
M src/soc/intel/broadwell/bootblock/pch.c
A src/soc/intel/broadwell/include/soc/bootblock.h
M src/soc/intel/broadwell/romstage/pch.c
M src/soc/intel/broadwell/romstage/romstage.c
M src/superio/ite/Makefile.inc
M src/superio/ite/it8772f/Makefile.inc
9 files changed, 111 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30385/1
diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc
index 01914ba..808dc50 100644
--- a/src/mainboard/google/jecht/Makefile.inc
+++ b/src/mainboard/google/jecht/Makefile.inc
@@ -23,7 +23,9 @@
romstage-y += variants/$(VARIANT_DIR)/pei_data.c
ramstage-y += variants/$(VARIANT_DIR)/pei_data.c
-romstage-y += led.c
+bootblock-y += led.c
+
+bootblock-y += bootblock.c
subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/google/jecht/bootblock.c b/src/mainboard/google/jecht/bootblock.c
new file mode 100644
index 0000000..6fa98bd
--- /dev/null
+++ b/src/mainboard/google/jecht/bootblock.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8772f/it8772f.h>
+#include <soc/bootblock.h>
+#include "onboard.h"
+
+void mainboard_pre_console_init(void)
+{
+ /* Early SuperIO setup */
+ it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV);
+ ite_kill_watchdog(IT8772F_GPIO_DEV);
+ ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+ /* Turn On Power LED */
+ set_power_led(LED_ON);
+
+}
diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c
index 7eccca9..0cd185e 100644
--- a/src/mainboard/google/jecht/romstage.c
+++ b/src/mainboard/google/jecht/romstage.c
@@ -21,8 +21,6 @@
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/romstage.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8772f/it8772f.h>
#include <mainboard/google/jecht/spd/spd.h>
#include <variant/gpio.h>
#include "onboard.h"
@@ -49,15 +47,3 @@
if (IS_ENABLED(CONFIG_CHROMEOS))
save_chromeos_gpios();
}
-
-void mainboard_pre_console_init(void)
-{
- /* Early SuperIO setup */
- it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV);
- ite_kill_watchdog(IT8772F_GPIO_DEV);
- ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- /* Turn On Power LED */
- set_power_led(LED_ON);
-
-}
diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c
index 9cd199f..1cf3f80 100644
--- a/src/soc/intel/broadwell/bootblock/pch.c
+++ b/src/soc/intel/broadwell/bootblock/pch.c
@@ -19,6 +19,9 @@
#include <soc/pci_devs.h>
#include <soc/rcba.h>
#include <soc/spi.h>
+#include <reg_script.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
#include <cpu/intel/car/bootblock.h>
/*
@@ -67,10 +70,61 @@
SPIBAR8(SPIBAR_SSFC + 2) = ssfc;
}
+const struct reg_script pch_early_init_script[] = {
+ /* Setup southbridge BARs */
+ REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1),
+ REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1),
+ REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN),
+ REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1),
+ REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN),
+
+ /* Set COM1/COM2 decode range */
+ REG_PCI_WRITE16(LPC_IO_DEC, 0x0010),
+ /* Enable legacy decode ranges */
+ REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |
+ COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN),
+
+ /* Enable IOAPIC */
+ REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100),
+ /* Read back for posted write */
+ REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC),
+
+ /* Set HPET address and enable it */
+ REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)),
+ /* Read back for posted write */
+ REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC),
+ /* Enable HPET to start counter */
+ REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)),
+
+ /* Disable reset */
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)),
+ /* TCO timer halt */
+ REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT),
+
+ /* Enable upper 128 bytes of CMOS */
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)),
+
+ /* Disable unused device (always) */
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS),
+
+ REG_SCRIPT_END
+};
+
+static void pch_early_lpc(void)
+{
+ reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script);
+}
+
void bootblock_early_southbridge_init(void)
{
map_rcba();
enable_spi_prefetch();
enable_port80_on_lpc();
set_spi_speed();
+ pch_early_lpc();
+ /* Call into mainboard pre console init. */
+ mainboard_pre_console_init();
}
+
+void __weak mainboard_pre_console_init(void) {}
+
diff --git a/src/soc/intel/broadwell/include/soc/bootblock.h b/src/soc/intel/broadwell/include/soc/bootblock.h
new file mode 100644
index 0000000..522d3cf
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/bootblock.h
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BROADWELL_BOOTBLOCK_H_
+#define _BROADWELL_BOOTBLOCK_H_
+
+void mainboard_pre_console_init(void);
+#endif
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c
index cffe71b..70ab5bc 100644
--- a/src/soc/intel/broadwell/romstage/pch.c
+++ b/src/soc/intel/broadwell/romstage/pch.c
@@ -28,46 +28,6 @@
#include <soc/smbus.h>
#include <soc/intel/broadwell/chip.h>
-const struct reg_script pch_early_init_script[] = {
- /* Setup southbridge BARs */
- REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1),
- REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1),
- REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN),
- REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1),
- REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN),
-
- /* Set COM1/COM2 decode range */
- REG_PCI_WRITE16(LPC_IO_DEC, 0x0010),
- /* Enable legacy decode ranges */
- REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |
- COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN),
-
- /* Enable IOAPIC */
- REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100),
- /* Read back for posted write */
- REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC),
-
- /* Set HPET address and enable it */
- REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)),
- /* Read back for posted write */
- REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC),
- /* Enable HPET to start counter */
- REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)),
-
- /* Disable reset */
- REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)),
- /* TCO timer halt */
- REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT),
-
- /* Enable upper 128 bytes of CMOS */
- REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)),
-
- /* Disable unused device (always) */
- REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS),
-
- REG_SCRIPT_END
-};
-
const struct reg_script pch_interrupt_init_script[] = {
/*
* GFX INTA -> PIRQA (MSI)
@@ -133,7 +93,6 @@
void pch_early_init(void)
{
- reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script);
reg_script_run_on_dev(PCH_DEV_LPC, pch_interrupt_init_script);
pch_enable_lpc();
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 8d75f50..8a4cf62 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -91,10 +91,6 @@
/* PCH Early Initialization */
pch_early_init();
- /* Call into mainboard pre console init. Needed to enable serial port
- on IT8772 */
- mainboard_pre_console_init();
-
/* Get power state */
rp.power_state = fill_power_state();
@@ -138,5 +134,3 @@
romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3);
}
-
-void __weak mainboard_pre_console_init(void) {}
diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc
index 382dbd7..e2127c2 100644
--- a/src/superio/ite/Makefile.inc
+++ b/src/superio/ite/Makefile.inc
@@ -14,6 +14,7 @@
##
## include generic ite pre-ram stage driver
+bootblock-$(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE) += common/early_serial.c
romstage-$(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE) += common/early_serial.c
## include generic ite environment controller driver
diff --git a/src/superio/ite/it8772f/Makefile.inc b/src/superio/ite/it8772f/Makefile.inc
index a0bf94d..6c06c36 100644
--- a/src/superio/ite/it8772f/Makefile.inc
+++ b/src/superio/ite/it8772f/Makefile.inc
@@ -14,6 +14,7 @@
## GNU General Public License for more details.
##
+bootblock-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c
romstage-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c
ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c
smm-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c
--
To view, visit https://review.coreboot.org/c/coreboot/+/30385
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde
Gerrit-Change-Number: 30385
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-MessageType: newchange
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