<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30385">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/broadwell: Enable LPC/SIO setup in bootblock<br><br>This allows for serial console during the bootblock.<br><br>Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/google/jecht/Makefile.inc<br>A src/mainboard/google/jecht/bootblock.c<br>M src/mainboard/google/jecht/romstage.c<br>M src/soc/intel/broadwell/bootblock/pch.c<br>A src/soc/intel/broadwell/include/soc/bootblock.h<br>M src/soc/intel/broadwell/romstage/pch.c<br>M src/soc/intel/broadwell/romstage/romstage.c<br>M src/superio/ite/Makefile.inc<br>M src/superio/ite/it8772f/Makefile.inc<br>9 files changed, 111 insertions(+), 62 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30385/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc</span><br><span>index 01914ba..808dc50 100644</span><br><span>--- a/src/mainboard/google/jecht/Makefile.inc</span><br><span>+++ b/src/mainboard/google/jecht/Makefile.inc</span><br><span>@@ -23,7 +23,9 @@</span><br><span> romstage-y += variants/$(VARIANT_DIR)/pei_data.c</span><br><span> ramstage-y += variants/$(VARIANT_DIR)/pei_data.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += led.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += led.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock.c</span><br><span> </span><br><span> subdirs-y += variants/$(VARIANT_DIR)</span><br><span> CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include</span><br><span>diff --git a/src/mainboard/google/jecht/bootblock.c b/src/mainboard/google/jecht/bootblock.c</span><br><span>new file mode 100644</span><br><span>index 0000000..6fa98bd</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/jecht/bootblock.c</span><br><span>@@ -0,0 +1,32 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2010 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/ite/common/ite.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/ite/it8772f/it8772f.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/bootblock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "onboard.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_pre_console_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Early SuperIO setup */</span><br><span style="color: hsl(120, 100%, 40%);">+ it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_kill_watchdog(IT8772F_GPIO_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Turn On Power LED */</span><br><span style="color: hsl(120, 100%, 40%);">+ set_power_led(LED_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c</span><br><span>index 7eccca9..0cd185e 100644</span><br><span>--- a/src/mainboard/google/jecht/romstage.c</span><br><span>+++ b/src/mainboard/google/jecht/romstage.c</span><br><span>@@ -21,8 +21,6 @@</span><br><span> #include <soc/pei_data.h></span><br><span> #include <soc/pei_wrapper.h></span><br><span> #include <soc/romstage.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <superio/ite/common/ite.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <superio/ite/it8772f/it8772f.h></span><br><span> #include <mainboard/google/jecht/spd/spd.h></span><br><span> #include <variant/gpio.h></span><br><span> #include "onboard.h"</span><br><span>@@ -49,15 +47,3 @@</span><br><span> if (IS_ENABLED(CONFIG_CHROMEOS))</span><br><span> save_chromeos_gpios();</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_pre_console_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Early SuperIO setup */</span><br><span style="color: hsl(0, 100%, 40%);">- it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV);</span><br><span style="color: hsl(0, 100%, 40%);">- ite_kill_watchdog(IT8772F_GPIO_DEV);</span><br><span style="color: hsl(0, 100%, 40%);">- ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Turn On Power LED */</span><br><span style="color: hsl(0, 100%, 40%);">- set_power_led(LED_ON);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c</span><br><span>index 9cd199f..1cf3f80 100644</span><br><span>--- a/src/soc/intel/broadwell/bootblock/pch.c</span><br><span>+++ b/src/soc/intel/broadwell/bootblock/pch.c</span><br><span>@@ -19,6 +19,9 @@</span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/rcba.h></span><br><span> #include <soc/spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <reg_script.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/romstage.h></span><br><span> #include <cpu/intel/car/bootblock.h></span><br><span> </span><br><span> /*</span><br><span>@@ -67,10 +70,61 @@</span><br><span> SPIBAR8(SPIBAR_SSFC + 2) = ssfc;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+const struct reg_script pch_early_init_script[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Setup southbridge BARs */</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1),</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1),</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN),</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1),</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set COM1/COM2 decode range */</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_PCI_WRITE16(LPC_IO_DEC, 0x0010),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable legacy decode ranges */</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |</span><br><span style="color: hsl(120, 100%, 40%);">+ COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable IOAPIC */</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Read back for posted write */</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set HPET address and enable it */</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Read back for posted write */</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable HPET to start counter */</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable reset */</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TCO timer halt */</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable upper 128 bytes of CMOS */</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable unused device (always) */</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_SCRIPT_END</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_early_lpc(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void bootblock_early_southbridge_init(void)</span><br><span> {</span><br><span> map_rcba();</span><br><span> enable_spi_prefetch();</span><br><span> enable_port80_on_lpc();</span><br><span> set_spi_speed();</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_early_lpc();</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Call into mainboard pre console init. */</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_pre_console_init();</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void __weak mainboard_pre_console_init(void) {}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/bootblock.h b/src/soc/intel/broadwell/include/soc/bootblock.h</span><br><span>new file mode 100644</span><br><span>index 0000000..522d3cf</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/bootblock.h</span><br><span>@@ -0,0 +1,20 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _BROADWELL_BOOTBLOCK_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _BROADWELL_BOOTBLOCK_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_pre_console_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c</span><br><span>index cffe71b..70ab5bc 100644</span><br><span>--- a/src/soc/intel/broadwell/romstage/pch.c</span><br><span>+++ b/src/soc/intel/broadwell/romstage/pch.c</span><br><span>@@ -28,46 +28,6 @@</span><br><span> #include <soc/smbus.h></span><br><span> #include <soc/intel/broadwell/chip.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const struct reg_script pch_early_init_script[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Setup southbridge BARs */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1),</span><br><span style="color: hsl(0, 100%, 40%);">- REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1),</span><br><span style="color: hsl(0, 100%, 40%);">- REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN),</span><br><span style="color: hsl(0, 100%, 40%);">- REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1),</span><br><span style="color: hsl(0, 100%, 40%);">- REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set COM1/COM2 decode range */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_PCI_WRITE16(LPC_IO_DEC, 0x0010),</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable legacy decode ranges */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |</span><br><span style="color: hsl(0, 100%, 40%);">- COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable IOAPIC */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100),</span><br><span style="color: hsl(0, 100%, 40%);">- /* Read back for posted write */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set HPET address and enable it */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)),</span><br><span style="color: hsl(0, 100%, 40%);">- /* Read back for posted write */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC),</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable HPET to start counter */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable reset */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)),</span><br><span style="color: hsl(0, 100%, 40%);">- /* TCO timer halt */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable upper 128 bytes of CMOS */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable unused device (always) */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- REG_SCRIPT_END</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> const struct reg_script pch_interrupt_init_script[] = {</span><br><span> /*</span><br><span> * GFX INTA -> PIRQA (MSI)</span><br><span>@@ -133,7 +93,6 @@</span><br><span> </span><br><span> void pch_early_init(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script);</span><br><span> reg_script_run_on_dev(PCH_DEV_LPC, pch_interrupt_init_script);</span><br><span> </span><br><span> pch_enable_lpc();</span><br><span>diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c</span><br><span>index 8d75f50..8a4cf62 100644</span><br><span>--- a/src/soc/intel/broadwell/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/broadwell/romstage/romstage.c</span><br><span>@@ -91,10 +91,6 @@</span><br><span> /* PCH Early Initialization */</span><br><span> pch_early_init();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Call into mainboard pre console init. Needed to enable serial port</span><br><span style="color: hsl(0, 100%, 40%);">- on IT8772 */</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_pre_console_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Get power state */</span><br><span> rp.power_state = fill_power_state();</span><br><span> </span><br><span>@@ -138,5 +134,3 @@</span><br><span> </span><br><span> romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3);</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void __weak mainboard_pre_console_init(void) {}</span><br><span>diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc</span><br><span>index 382dbd7..e2127c2 100644</span><br><span>--- a/src/superio/ite/Makefile.inc</span><br><span>+++ b/src/superio/ite/Makefile.inc</span><br><span>@@ -14,6 +14,7 @@</span><br><span> ##</span><br><span> </span><br><span> ## include generic ite pre-ram stage driver</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE) += common/early_serial.c</span><br><span> romstage-$(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE) += common/early_serial.c</span><br><span> </span><br><span> ## include generic ite environment controller driver</span><br><span>diff --git a/src/superio/ite/it8772f/Makefile.inc b/src/superio/ite/it8772f/Makefile.inc</span><br><span>index a0bf94d..6c06c36 100644</span><br><span>--- a/src/superio/ite/it8772f/Makefile.inc</span><br><span>+++ b/src/superio/ite/it8772f/Makefile.inc</span><br><span>@@ -14,6 +14,7 @@</span><br><span> ## GNU General Public License for more details.</span><br><span> ##</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c</span><br><span> romstage-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c</span><br><span> ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c</span><br><span> smm-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30385">change 30385</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde </div>
<div style="display:none"> Gerrit-Change-Number: 30385 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>