[coreboot-gerrit] Change in ...coreboot[master]: mb/google/hatch: Enable H1 TPM support over SPI interface
Subrata Banik (Code Review)
gerrit at coreboot.org
Fri Dec 21 05:42:34 CET 2018
Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30210 )
Change subject: mb/google/hatch: Enable H1 TPM support over SPI interface
......................................................................
mb/google/hatch: Enable H1 TPM support over SPI interface
Add code support to enable H1 TPM interfaced to SOC on GSPI0.
The TPM interrupt is mapped to GPP_C21.
BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot
Change-Id: Ib63a0b473f632d91745102ebd01993e8d65b9552
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
Reviewed-on: https://review.coreboot.org/c/30210
Reviewed-by: Furquan Shaikh <furquan at google.com>
Reviewed-by: Subrata Banik <subrata.banik at intel.com>
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
---
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/mainboard/google/hatch/variants/baseboard/gpio.c
3 files changed, 71 insertions(+), 11 deletions(-)
Approvals:
build bot (Jenkins): Verified
Furquan Shaikh: Looks good to me, approved
Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 7acfd09..1c0208f 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -10,14 +10,13 @@
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS
- select MAINBOARD_HAS_I2C_TPM_CR50
+ select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2
select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK
select SOC_INTEL_COFFEELAKE
select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP
- select TPM2
if BOARD_GOOGLE_BASEBOARD_HATCH
@@ -29,6 +28,10 @@
select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
select GBB_FLAG_FORCE_MANUAL_RECOVERY
+config DEVICETREE
+ string
+ default "variants/baseboard/devicetree.cb"
+
config DIMM_MAX
int
default 2
@@ -37,6 +40,9 @@
int
default 512
+config DRIVER_TPM_SPI_BUS
+ default 0x1
+
config GBB_HWID
string
depends on CHROMEOS
@@ -62,18 +68,18 @@
int
default 8
-config VARIANT_DIR
- string
- default "hatch" if BOARD_GOOGLE_HATCH
-
-config DEVICETREE
- string
- default "variants/baseboard/devicetree.cb"
-
config OVERRIDE_DEVICETREE
string
default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_HATCH
+config TPM_TIS_ACPI_INTERRUPT
+ int
+ default 53 # GPE0_DW1_21 (GPP_C21)
+
+config VARIANT_DIR
+ string
+ default "hatch" if BOARD_GOOGLE_HATCH
+
config VBOOT
select HAS_RECOVERY_MRC_CACHE
select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 88df092..4fe0c4c 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -1,4 +1,31 @@
chip soc/intel/cannonlake
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ # DW1 is used by:
+ # - GPP_C21 - H1_PCH_INT_ODL
+ register "gpe0_dw0" = "PMC_GPP_A"
+ register "gpe0_dw1" = "PMC_GPP_C"
+ register "gpe0_dw2" = "PMC_GPP_D"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ }"
+
device domain 0 on
device pci 00.0 off end # Host Bridge
device pci 02.0 off end # Integrated Graphics Device
@@ -39,7 +66,14 @@
device pci 1d.4 off end # PCI Express Port 13 (x4)
device pci 1e.0 off end # UART #0
device pci 1e.1 off end # UART #1
- device pci 1e.2 off end # GSPI #0
+ device pci 1e.2 on
+ chip drivers/spi/acpi
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "compat_string" = ""google,cr50""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)"
+ device spi 0 on end
+ end
+ end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 off end # LPC/eSPI
device pci 1f.1 off end # P2SB
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index 6f6b9d2..2517a58 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -19,6 +19,16 @@
#include <commonlib/helpers.h>
static const struct pad_config gpio_table[] = {
+ /* H1_SLAVE_SPI_CS_L */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+ /* H1_SLAVE_SPI_CLK */
+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+ /* H1_SLAVE_SPI_MISO_R */
+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+ /* H1_SLAVE_SPI_MOSI_R */
+ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+ /* H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT),
};
const struct pad_config *__weak variant_gpio_table(size_t *num)
@@ -29,6 +39,16 @@
/* GPIOs needed prior to ramstage. */
static const struct pad_config early_gpio_table[] = {
+ /* H1_SLAVE_SPI_CS_L */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+ /* H1_SLAVE_SPI_CLK */
+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+ /* H1_SLAVE_SPI_MISO_R */
+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+ /* H1_SLAVE_SPI_MOSI_R */
+ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+ /* H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT),
};
const struct pad_config *__weak variant_early_gpio_table(size_t *num)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib63a0b473f632d91745102ebd01993e8d65b9552
Gerrit-Change-Number: 30210
Gerrit-PatchSet: 15
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Shelley Chen <shchen at google.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-MessageType: merged
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