<p>Subrata Banik <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30210">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Furquan Shaikh: Looks good to me, approved
Subrata Banik: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/hatch: Enable H1 TPM support over SPI interface<br><br>Add code support to enable H1 TPM interfaced to SOC on GSPI0.<br>The TPM interrupt is mapped to GPP_C21.<br><br>BUG=b:120914069<br>TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot<br><br>Change-Id: Ib63a0b473f632d91745102ebd01993e8d65b9552<br>Signed-off-by: Aamir Bohra <aamir.bohra@intel.com><br>Reviewed-on: https://review.coreboot.org/c/30210<br>Reviewed-by: Furquan Shaikh <furquan@google.com><br>Reviewed-by: Subrata Banik <subrata.banik@intel.com><br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>---<br>M src/mainboard/google/hatch/Kconfig<br>M src/mainboard/google/hatch/variants/baseboard/devicetree.cb<br>M src/mainboard/google/hatch/variants/baseboard/gpio.c<br>3 files changed, 71 insertions(+), 11 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig</span><br><span>index 7acfd09..1c0208f 100644</span><br><span>--- a/src/mainboard/google/hatch/Kconfig</span><br><span>+++ b/src/mainboard/google/hatch/Kconfig</span><br><span>@@ -10,14 +10,13 @@</span><br><span> select HAVE_ACPI_RESUME</span><br><span> select HAVE_ACPI_TABLES</span><br><span> select MAINBOARD_HAS_CHROMEOS</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_I2C_TPM_CR50</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_SPI_TPM_CR50</span><br><span> select MAINBOARD_HAS_TPM2</span><br><span> select SOC_INTEL_CANNONLAKE_MEMCFG_INIT</span><br><span> select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK</span><br><span> select SOC_INTEL_COFFEELAKE</span><br><span> select SPD_READ_BY_WORD</span><br><span> select SYSTEM_TYPE_LAPTOP</span><br><span style="color: hsl(0, 100%, 40%);">- select TPM2</span><br><span> </span><br><span> if BOARD_GOOGLE_BASEBOARD_HATCH</span><br><span> </span><br><span>@@ -29,6 +28,10 @@</span><br><span> select GBB_FLAG_FORCE_DEV_BOOT_LEGACY</span><br><span> select GBB_FLAG_FORCE_MANUAL_RECOVERY</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config DEVICETREE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/baseboard/devicetree.cb"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config DIMM_MAX</span><br><span> int</span><br><span> default 2</span><br><span>@@ -37,6 +40,9 @@</span><br><span> int</span><br><span> default 512</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config DRIVER_TPM_SPI_BUS</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config GBB_HWID</span><br><span> string</span><br><span> depends on CHROMEOS</span><br><span>@@ -62,18 +68,18 @@</span><br><span> int</span><br><span> default 8</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config VARIANT_DIR</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "hatch" if BOARD_GOOGLE_HATCH</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config DEVICETREE</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "variants/baseboard/devicetree.cb"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config OVERRIDE_DEVICETREE</span><br><span> string</span><br><span> default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_HATCH</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config TPM_TIS_ACPI_INTERRUPT</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 53 # GPE0_DW1_21 (GPP_C21)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VARIANT_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "hatch" if BOARD_GOOGLE_HATCH</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config VBOOT</span><br><span> select HAS_RECOVERY_MRC_CACHE</span><br><span> select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN</span><br><span>diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb</span><br><span>index 88df092..4fe0c4c 100644</span><br><span>--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb</span><br><span>@@ -1,4 +1,31 @@</span><br><span> chip soc/intel/cannonlake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPE configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ # Note that GPE events called out in ASL code rely on this</span><br><span style="color: hsl(120, 100%, 40%);">+ # route. i.e. If this route changes then the affected GPE</span><br><span style="color: hsl(120, 100%, 40%);">+ # offset bits also need to be changed.</span><br><span style="color: hsl(120, 100%, 40%);">+ # DW1 is used by:</span><br><span style="color: hsl(120, 100%, 40%);">+ # - GPP_C21 - H1_PCH_INT_ODL</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw0" = "PMC_GPP_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "PMC_GPP_C"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw2" = "PMC_GPP_D"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Intel Common SoC Config</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Field | Value |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| GSPI0 | cr50 TPM. Early init is |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| | required to set up a BAR |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| | for TPM communication |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| | before memory is up |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "common_soc_config" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .gspi[0] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed_mhz = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .early_init = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> device domain 0 on</span><br><span> device pci 00.0 off end # Host Bridge</span><br><span> device pci 02.0 off end # Integrated Graphics Device</span><br><span>@@ -39,7 +66,14 @@</span><br><span> device pci 1d.4 off end # PCI Express Port 13 (x4)</span><br><span> device pci 1e.0 off end # UART #0</span><br><span> device pci 1e.1 off end # UART #1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1e.2 off end # GSPI #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.2 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/spi/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = "ACPI_DT_NAMESPACE_HID"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "compat_string" = ""google,cr50""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device spi 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # GSPI #0</span><br><span> device pci 1e.3 off end # GSPI #1</span><br><span> device pci 1f.0 off end # LPC/eSPI</span><br><span> device pci 1f.1 off end # P2SB</span><br><span>diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c</span><br><span>index 6f6b9d2..2517a58 100644</span><br><span>--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c</span><br><span>@@ -19,6 +19,16 @@</span><br><span> #include <commonlib/helpers.h></span><br><span> </span><br><span> static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H1_SLAVE_SPI_CS_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H1_SLAVE_SPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H1_SLAVE_SPI_MISO_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H1_SLAVE_SPI_MOSI_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT),</span><br><span> };</span><br><span> </span><br><span> const struct pad_config *__weak variant_gpio_table(size_t *num)</span><br><span>@@ -29,6 +39,16 @@</span><br><span> </span><br><span> /* GPIOs needed prior to ramstage. */</span><br><span> static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H1_SLAVE_SPI_CS_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H1_SLAVE_SPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H1_SLAVE_SPI_MISO_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H1_SLAVE_SPI_MOSI_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT),</span><br><span> };</span><br><span> </span><br><span> const struct pad_config *__weak variant_early_gpio_table(size_t *num)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30210">change 30210</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ib63a0b473f632d91745102ebd01993e8d65b9552 </div>
<div style="display:none"> Gerrit-Change-Number: 30210 </div>
<div style="display:none"> Gerrit-PatchSet: 15 </div>
<div style="display:none"> Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Shelley Chen <shchen@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>