[coreboot-gerrit] Change in ...coreboot[master]: cpu/intel/haswell: Remove the romcc code
Arthur Heymans (Code Review)
gerrit at coreboot.org
Wed Dec 19 17:04:13 CET 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30316
Change subject: cpu/intel/haswell: Remove the romcc code
......................................................................
cpu/intel/haswell: Remove the romcc code
This also renames the bootblock_gcc.c files to bootblock.c.
Change-Id: I66387ae13939df41abdba9fb0015774e363100e4
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/haswell/Makefile.inc
M src/cpu/intel/haswell/bootblock.c
D src/cpu/intel/haswell/bootblock_gcc.c
M src/northbridge/intel/haswell/Makefile.inc
M src/northbridge/intel/haswell/bootblock.c
D src/northbridge/intel/haswell/bootblock_gcc.c
M src/southbridge/intel/lynxpoint/Makefile.inc
M src/southbridge/intel/lynxpoint/bootblock.c
D src/southbridge/intel/lynxpoint/bootblock_gcc.c
9 files changed, 17 insertions(+), 282 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/30316/1
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index 1133d6a..80264cf 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -21,7 +21,7 @@
bootblock-y += ../car/non-evict/cache_as_ram.S
bootblock-y += ../car/bootblock.c
-bootblock-y += bootblock_gcc.c
+bootblock-y += bootblock.c
bootblock-y += ../microcode/microcode_asm.S
postcar-y += ../car/non-evict/exit_car.S
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c
index 3a306b5..7baa2a8 100644
--- a/src/cpu/intel/haswell/bootblock.c
+++ b/src/cpu/intel/haswell/bootblock.c
@@ -14,7 +14,7 @@
*/
#include <stdint.h>
-#include <cpu/x86/cache.h>
+#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <arch/io.h>
@@ -23,41 +23,8 @@
#include <cpu/intel/microcode/microcode.c>
#include "haswell.h"
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)
-/* Needed for RCBA access to set Soft Reset Data register */
#include <southbridge/intel/lynxpoint/pch.h>
-#else
-#error "CPU must be paired with Intel LynxPoint southbridge"
-#endif
-
-static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
- unsigned int type)
-
-{
- /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
- /* FIXME: It only support 4G less range */
- msr_t basem, maskm;
- basem.lo = base | type;
- basem.hi = 0;
- wrmsr(MTRR_PHYS_BASE(reg), basem);
- maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
- maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
- wrmsr(MTRR_PHYS_MASK(reg), maskm);
-}
-
-static void enable_rom_caching(void)
-{
- msr_t msr;
-
- disable_cache();
- set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
- enable_cache();
-
- /* Enable Variable MTRRs */
- msr.hi = 0x00000000;
- msr.lo = 0x00000800;
- wrmsr(MTRR_DEF_TYPE_MSR, msr);
-}
+#include <cpu/intel/car/bootblock.h>
static void set_flex_ratio_to_tdp_nominal(void)
{
@@ -105,26 +72,8 @@
halt();
}
-static void check_for_clean_reset(void)
-{
- msr_t msr;
- msr = rdmsr(MTRR_DEF_TYPE_MSR);
-
- /* Use the MTRR default type MSR as a proxy for detecting INIT#.
- * Reset the system if any known bits are set in that MSR. That is
- * an indication of the CPU not being properly reset. */
- if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) {
- outb(0x0, 0xcf9);
- outb(0x6, 0xcf9);
- halt();
- }
-}
-
-static void bootblock_cpu_init(void)
+void bootblock_early_cpu_init(void)
{
/* Set flex ratio and reset if needed */
set_flex_ratio_to_tdp_nominal();
- check_for_clean_reset();
- enable_rom_caching();
- intel_update_microcode_from_cbfs();
}
diff --git a/src/cpu/intel/haswell/bootblock_gcc.c b/src/cpu/intel/haswell/bootblock_gcc.c
deleted file mode 100644
index 7baa2a8..0000000
--- a/src/cpu/intel/haswell/bootblock_gcc.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <arch/io.h>
-#include <halt.h>
-
-#include <cpu/intel/microcode/microcode.c>
-#include "haswell.h"
-
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <cpu/intel/car/bootblock.h>
-
-static void set_flex_ratio_to_tdp_nominal(void)
-{
- msr_t flex_ratio, msr;
- u32 soft_reset;
- u8 nominal_ratio;
-
- /* Check for Flex Ratio support */
- flex_ratio = rdmsr(MSR_FLEX_RATIO);
- if (!(flex_ratio.lo & FLEX_RATIO_EN))
- return;
-
- /* Check for >0 configurable TDPs */
- msr = rdmsr(MSR_PLATFORM_INFO);
- if (((msr.hi >> 1) & 3) == 0)
- return;
-
- /* Use nominal TDP ratio for flex ratio */
- msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
- nominal_ratio = msr.lo & 0xff;
-
- /* See if flex ratio is already set to nominal TDP ratio */
- if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
- return;
-
- /* Set flex ratio to nominal TDP ratio */
- flex_ratio.lo &= ~0xff00;
- flex_ratio.lo |= nominal_ratio << 8;
- flex_ratio.lo |= FLEX_RATIO_LOCK;
- wrmsr(MSR_FLEX_RATIO, flex_ratio);
-
- /* Set flex ratio in soft reset data register bits 11:6.
- * RCBA region is enabled in southbridge bootblock */
- soft_reset = RCBA32(SOFT_RESET_DATA);
- soft_reset &= ~(0x3f << 6);
- soft_reset |= (nominal_ratio & 0x3f) << 6;
- RCBA32(SOFT_RESET_DATA) = soft_reset;
-
- /* Set soft reset control to use register value */
- RCBA32_OR(SOFT_RESET_CTRL, 1);
-
- /* Issue warm reset, will be "CPU only" due to soft reset data */
- outb(0x0, 0xcf9);
- outb(0x6, 0xcf9);
- halt();
-}
-
-void bootblock_early_cpu_init(void)
-{
- /* Set flex ratio and reset if needed */
- set_flex_ratio_to_tdp_nominal();
-}
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index 1566c73..7abbcca 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -15,7 +15,7 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_HASWELL),y)
-bootblock-y += bootblock_gcc.c
+bootblock-y += bootblock.c
ramstage-y += ram_calc.c
ramstage-y += northbridge.c
@@ -28,7 +28,6 @@
romstage-y += raminit.c
romstage-y += early_init.c
romstage-y += report_platform.c
-romstage-y += ../../../arch/x86/walkcbfs.S
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index a25f363..e907bca 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -12,11 +12,10 @@
*/
#include <arch/io.h>
+#include <cpu/intel/car/bootblock.h>
+#include "haswell.h"
-/* Just re-define this instead of including haswell.h. It blows up romcc. */
-#define PCIEXBAR 0x60
-
-static void bootblock_northbridge_init(void)
+void bootblock_early_northbridge_init(void)
{
uint32_t reg;
@@ -33,7 +32,7 @@
* 4GiB.
*/
reg = 0;
- pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg);
+ pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR + 4, reg);
reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
- pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg);
+ pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg);
}
diff --git a/src/northbridge/intel/haswell/bootblock_gcc.c b/src/northbridge/intel/haswell/bootblock_gcc.c
deleted file mode 100644
index e907bca..0000000
--- a/src/northbridge/intel/haswell/bootblock_gcc.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <cpu/intel/car/bootblock.h>
-#include "haswell.h"
-
-void bootblock_early_northbridge_init(void)
-{
- uint32_t reg;
-
- /*
- * The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
- * to true. That way all subsequent non-explicit config accesses use
- * MCFG. This code also assumes that bootblock_northbridge_init() is
- * the first thing called in the non-asm boot block code. The final
- * assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
- *
- * The PCIEXBAR is assumed to live in the memory mapped IO space under
- * 4GiB.
- */
- reg = 0;
- pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR + 4, reg);
- reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
- pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg);
-}
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 5196c3c..45949b4 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -15,7 +15,7 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
-bootblock-y += bootblock_gcc.c
+bootblock-y += bootblock.c
ramstage-y += pch.c
ramstage-y += azalia.c
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index 20d0ee3..85ccc27 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -14,20 +14,9 @@
*/
#include <arch/io.h>
-#include <cpu/x86/tsc.h>
+#include <cpu/intel/car/bootblock.h>
#include "pch.h"
-static void store_initial_timestamp(void)
-{
- /* On Cougar Point we have two 32bit scratchpad registers available:
- * D0:F0 0xdc (SKPAD)
- * D31:F2 0xd0 (SATA SP)
- */
- tsc_t tsc = rdtsc();
- pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
- pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
-}
-
/*
* Enable Prefetching and Caching.
*/
@@ -54,7 +43,7 @@
static void enable_port80_on_lpc(void)
{
- /* Enable port 80 POST on LPC. The chipset does this by deafult,
+ /* Enable port 80 POST on LPC. The chipset does this by default,
* but it doesn't appear to hurt anything. */
u32 gcs = RCBA32(GCS);
gcs = gcs & ~0x4;
@@ -81,10 +70,8 @@
SPIBAR8(SSFC + 2) = ssfc;
}
-static void bootblock_southbridge_init(void)
+void bootblock_early_southbridge_init(void)
{
- store_initial_timestamp();
-
map_rcba();
enable_spi_prefetch();
enable_port80_on_lpc();
@@ -92,4 +79,7 @@
/* Enable upper 128bytes of CMOS */
RCBA32(RC) = (1 << 2);
+
+ pch_enable_lpc();
+ mainboard_config_superio();
}
diff --git a/src/southbridge/intel/lynxpoint/bootblock_gcc.c b/src/southbridge/intel/lynxpoint/bootblock_gcc.c
deleted file mode 100644
index 85ccc27..0000000
--- a/src/southbridge/intel/lynxpoint/bootblock_gcc.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <cpu/intel/car/bootblock.h>
-#include "pch.h"
-
-/*
- * Enable Prefetching and Caching.
- */
-static void enable_spi_prefetch(void)
-{
- u8 reg8;
- pci_devfn_t dev;
-
- dev = PCI_DEV(0, 0x1f, 0);
-
- reg8 = pci_read_config8(dev, 0xdc);
- reg8 &= ~(3 << 2);
- reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
- pci_write_config8(dev, 0xdc, reg8);
-}
-
-
-static void map_rcba(void)
-{
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
-
- pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
-}
-
-static void enable_port80_on_lpc(void)
-{
- /* Enable port 80 POST on LPC. The chipset does this by default,
- * but it doesn't appear to hurt anything. */
- u32 gcs = RCBA32(GCS);
- gcs = gcs & ~0x4;
- RCBA32(GCS) = gcs;
-}
-
-static void set_spi_speed(void)
-{
- u32 fdod;
- u8 ssfc;
-
- /* Observe SPI Descriptor Component Section 0 */
- SPIBAR32(FDOC) = 0x1000;
-
- /* Extract the Write/Erase SPI Frequency from descriptor */
- fdod = SPIBAR32(FDOD);
- fdod >>= 24;
- fdod &= 7;
-
- /* Set Software Sequence frequency to match */
- ssfc = SPIBAR8(SSFC + 2);
- ssfc &= ~7;
- ssfc |= fdod;
- SPIBAR8(SSFC + 2) = ssfc;
-}
-
-void bootblock_early_southbridge_init(void)
-{
- map_rcba();
- enable_spi_prefetch();
- enable_port80_on_lpc();
- set_spi_speed();
-
- /* Enable upper 128bytes of CMOS */
- RCBA32(RC) = (1 << 2);
-
- pch_enable_lpc();
- mainboard_config_superio();
-}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I66387ae13939df41abdba9fb0015774e363100e4
Gerrit-Change-Number: 30316
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-MessageType: newchange
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