<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30316">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel/haswell: Remove the romcc code<br><br>This also renames the bootblock_gcc.c files to bootblock.c.<br><br>Change-Id: I66387ae13939df41abdba9fb0015774e363100e4<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/haswell/Makefile.inc<br>M src/cpu/intel/haswell/bootblock.c<br>D src/cpu/intel/haswell/bootblock_gcc.c<br>M src/northbridge/intel/haswell/Makefile.inc<br>M src/northbridge/intel/haswell/bootblock.c<br>D src/northbridge/intel/haswell/bootblock_gcc.c<br>M src/southbridge/intel/lynxpoint/Makefile.inc<br>M src/southbridge/intel/lynxpoint/bootblock.c<br>D src/southbridge/intel/lynxpoint/bootblock_gcc.c<br>9 files changed, 17 insertions(+), 282 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/30316/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc</span><br><span>index 1133d6a..80264cf 100644</span><br><span>--- a/src/cpu/intel/haswell/Makefile.inc</span><br><span>+++ b/src/cpu/intel/haswell/Makefile.inc</span><br><span>@@ -21,7 +21,7 @@</span><br><span> </span><br><span> bootblock-y += ../car/non-evict/cache_as_ram.S</span><br><span> bootblock-y += ../car/bootblock.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += bootblock_gcc.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock.c</span><br><span> bootblock-y += ../microcode/microcode_asm.S</span><br><span> </span><br><span> postcar-y += ../car/non-evict/exit_car.S</span><br><span>diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c</span><br><span>index 3a306b5..7baa2a8 100644</span><br><span>--- a/src/cpu/intel/haswell/bootblock.c</span><br><span>+++ b/src/cpu/intel/haswell/bootblock.c</span><br><span>@@ -14,7 +14,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <stdint.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/cpu.h></span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <arch/io.h></span><br><span>@@ -23,41 +23,8 @@</span><br><span> #include <cpu/intel/microcode/microcode.c></span><br><span> #include "haswell.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)</span><br><span style="color: hsl(0, 100%, 40%);">-/* Needed for RCBA access to set Soft Reset Data register */</span><br><span> #include <southbridge/intel/lynxpoint/pch.h></span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-#error "CPU must be paired with Intel LynxPoint southbridge"</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int type)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* FIXME: It only support 4G less range */</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t basem, maskm;</span><br><span style="color: hsl(0, 100%, 40%);">- basem.lo = base | type;</span><br><span style="color: hsl(0, 100%, 40%);">- basem.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MTRR_PHYS_BASE(reg), basem);</span><br><span style="color: hsl(0, 100%, 40%);">- maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;</span><br><span style="color: hsl(0, 100%, 40%);">- maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MTRR_PHYS_MASK(reg), maskm);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_rom_caching(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- disable_cache();</span><br><span style="color: hsl(0, 100%, 40%);">- set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(0, 100%, 40%);">- enable_cache();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable Variable MTRRs */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0x00000000;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0x00000800;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MTRR_DEF_TYPE_MSR, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/car/bootblock.h></span><br><span> </span><br><span> static void set_flex_ratio_to_tdp_nominal(void)</span><br><span> {</span><br><span>@@ -105,26 +72,8 @@</span><br><span> halt();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void check_for_clean_reset(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MTRR_DEF_TYPE_MSR);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Use the MTRR default type MSR as a proxy for detecting INIT#.</span><br><span style="color: hsl(0, 100%, 40%);">- * Reset the system if any known bits are set in that MSR. That is</span><br><span style="color: hsl(0, 100%, 40%);">- * an indication of the CPU not being properly reset. */</span><br><span style="color: hsl(0, 100%, 40%);">- if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) {</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0x0, 0xcf9);</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0x6, 0xcf9);</span><br><span style="color: hsl(0, 100%, 40%);">- halt();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void bootblock_cpu_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_early_cpu_init(void)</span><br><span> {</span><br><span> /* Set flex ratio and reset if needed */</span><br><span> set_flex_ratio_to_tdp_nominal();</span><br><span style="color: hsl(0, 100%, 40%);">- check_for_clean_reset();</span><br><span style="color: hsl(0, 100%, 40%);">- enable_rom_caching();</span><br><span style="color: hsl(0, 100%, 40%);">- intel_update_microcode_from_cbfs();</span><br><span> }</span><br><span>diff --git a/src/cpu/intel/haswell/bootblock_gcc.c b/src/cpu/intel/haswell/bootblock_gcc.c</span><br><span>deleted file mode 100644</span><br><span>index 7baa2a8..0000000</span><br><span>--- a/src/cpu/intel/haswell/bootblock_gcc.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,79 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2011 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdint.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/cpu.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <halt.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/intel/microcode/microcode.c></span><br><span style="color: hsl(0, 100%, 40%);">-#include "haswell.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/lynxpoint/pch.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/intel/car/bootblock.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void set_flex_ratio_to_tdp_nominal(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t flex_ratio, msr;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 soft_reset;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 nominal_ratio;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Check for Flex Ratio support */</span><br><span style="color: hsl(0, 100%, 40%);">- flex_ratio = rdmsr(MSR_FLEX_RATIO);</span><br><span style="color: hsl(0, 100%, 40%);">- if (!(flex_ratio.lo & FLEX_RATIO_EN))</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Check for >0 configurable TDPs */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_PLATFORM_INFO);</span><br><span style="color: hsl(0, 100%, 40%);">- if (((msr.hi >> 1) & 3) == 0)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Use nominal TDP ratio for flex ratio */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);</span><br><span style="color: hsl(0, 100%, 40%);">- nominal_ratio = msr.lo & 0xff;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* See if flex ratio is already set to nominal TDP ratio */</span><br><span style="color: hsl(0, 100%, 40%);">- if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set flex ratio to nominal TDP ratio */</span><br><span style="color: hsl(0, 100%, 40%);">- flex_ratio.lo &= ~0xff00;</span><br><span style="color: hsl(0, 100%, 40%);">- flex_ratio.lo |= nominal_ratio << 8;</span><br><span style="color: hsl(0, 100%, 40%);">- flex_ratio.lo |= FLEX_RATIO_LOCK;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_FLEX_RATIO, flex_ratio);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set flex ratio in soft reset data register bits 11:6.</span><br><span style="color: hsl(0, 100%, 40%);">- * RCBA region is enabled in southbridge bootblock */</span><br><span style="color: hsl(0, 100%, 40%);">- soft_reset = RCBA32(SOFT_RESET_DATA);</span><br><span style="color: hsl(0, 100%, 40%);">- soft_reset &= ~(0x3f << 6);</span><br><span style="color: hsl(0, 100%, 40%);">- soft_reset |= (nominal_ratio & 0x3f) << 6;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(SOFT_RESET_DATA) = soft_reset;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set soft reset control to use register value */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32_OR(SOFT_RESET_CTRL, 1);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Issue warm reset, will be "CPU only" due to soft reset data */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0x0, 0xcf9);</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0x6, 0xcf9);</span><br><span style="color: hsl(0, 100%, 40%);">- halt();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_early_cpu_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set flex ratio and reset if needed */</span><br><span style="color: hsl(0, 100%, 40%);">- set_flex_ratio_to_tdp_nominal();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc</span><br><span>index 1566c73..7abbcca 100644</span><br><span>--- a/src/northbridge/intel/haswell/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/haswell/Makefile.inc</span><br><span>@@ -15,7 +15,7 @@</span><br><span> </span><br><span> ifeq ($(CONFIG_NORTHBRIDGE_INTEL_HASWELL),y)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += bootblock_gcc.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock.c</span><br><span> </span><br><span> ramstage-y += ram_calc.c</span><br><span> ramstage-y += northbridge.c</span><br><span>@@ -28,7 +28,6 @@</span><br><span> romstage-y += raminit.c</span><br><span> romstage-y += early_init.c</span><br><span> romstage-y += report_platform.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += ../../../arch/x86/walkcbfs.S</span><br><span> </span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c</span><br><span>index a25f363..e907bca 100644</span><br><span>--- a/src/northbridge/intel/haswell/bootblock.c</span><br><span>+++ b/src/northbridge/intel/haswell/bootblock.c</span><br><span>@@ -12,11 +12,10 @@</span><br><span> */</span><br><span> </span><br><span> #include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/car/bootblock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "haswell.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Just re-define this instead of including haswell.h. It blows up romcc. */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCIEXBAR 0x60</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void bootblock_northbridge_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_early_northbridge_init(void)</span><br><span> {</span><br><span> uint32_t reg;</span><br><span> </span><br><span>@@ -33,7 +32,7 @@</span><br><span> * 4GiB.</span><br><span> */</span><br><span> reg = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR + 4, reg);</span><br><span> reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg);</span><br><span> }</span><br><span>diff --git a/src/northbridge/intel/haswell/bootblock_gcc.c b/src/northbridge/intel/haswell/bootblock_gcc.c</span><br><span>deleted file mode 100644</span><br><span>index e907bca..0000000</span><br><span>--- a/src/northbridge/intel/haswell/bootblock_gcc.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,38 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/intel/car/bootblock.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "haswell.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_early_northbridge_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t reg;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * The "io" variant of the config access is explicitly used to</span><br><span style="color: hsl(0, 100%, 40%);">- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to</span><br><span style="color: hsl(0, 100%, 40%);">- * to true. That way all subsequent non-explicit config accesses use</span><br><span style="color: hsl(0, 100%, 40%);">- * MCFG. This code also assumes that bootblock_northbridge_init() is</span><br><span style="color: hsl(0, 100%, 40%);">- * the first thing called in the non-asm boot block code. The final</span><br><span style="color: hsl(0, 100%, 40%);">- * assumption is that no assembly code is using the</span><br><span style="color: hsl(0, 100%, 40%);">- * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * The PCIEXBAR is assumed to live in the memory mapped IO space under</span><br><span style="color: hsl(0, 100%, 40%);">- * 4GiB.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- reg = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR + 4, reg);</span><br><span style="color: hsl(0, 100%, 40%);">- reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc</span><br><span>index 5196c3c..45949b4 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/Makefile.inc</span><br><span>+++ b/src/southbridge/intel/lynxpoint/Makefile.inc</span><br><span>@@ -15,7 +15,7 @@</span><br><span> </span><br><span> ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += bootblock_gcc.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock.c</span><br><span> </span><br><span> ramstage-y += pch.c</span><br><span> ramstage-y += azalia.c</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c</span><br><span>index 20d0ee3..85ccc27 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/bootblock.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/bootblock.c</span><br><span>@@ -14,20 +14,9 @@</span><br><span> */</span><br><span> </span><br><span> #include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/tsc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/car/bootblock.h></span><br><span> #include "pch.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void store_initial_timestamp(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* On Cougar Point we have two 32bit scratchpad registers available:</span><br><span style="color: hsl(0, 100%, 40%);">- * D0:F0 0xdc (SKPAD)</span><br><span style="color: hsl(0, 100%, 40%);">- * D31:F2 0xd0 (SATA SP)</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- tsc_t tsc = rdtsc();</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /*</span><br><span> * Enable Prefetching and Caching.</span><br><span> */</span><br><span>@@ -54,7 +43,7 @@</span><br><span> </span><br><span> static void enable_port80_on_lpc(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable port 80 POST on LPC. The chipset does this by deafult,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable port 80 POST on LPC. The chipset does this by default,</span><br><span> * but it doesn't appear to hurt anything. */</span><br><span> u32 gcs = RCBA32(GCS);</span><br><span> gcs = gcs & ~0x4;</span><br><span>@@ -81,10 +70,8 @@</span><br><span> SPIBAR8(SSFC + 2) = ssfc;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void bootblock_southbridge_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_early_southbridge_init(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- store_initial_timestamp();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> map_rcba();</span><br><span> enable_spi_prefetch();</span><br><span> enable_port80_on_lpc();</span><br><span>@@ -92,4 +79,7 @@</span><br><span> </span><br><span> /* Enable upper 128bytes of CMOS */</span><br><span> RCBA32(RC) = (1 << 2);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_enable_lpc();</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_config_superio();</span><br><span> }</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/bootblock_gcc.c b/src/southbridge/intel/lynxpoint/bootblock_gcc.c</span><br><span>deleted file mode 100644</span><br><span>index 85ccc27..0000000</span><br><span>--- a/src/southbridge/intel/lynxpoint/bootblock_gcc.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,85 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2011 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/intel/car/bootblock.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "pch.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * Enable Prefetching and Caching.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_spi_prefetch(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u8 reg8;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_devfn_t dev;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dev = PCI_DEV(0, 0x1f, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(dev, 0xdc);</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 &= ~(3 << 2);</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 |= (2 << 2); /* Prefetching and Caching Enabled */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, 0xdc, reg8);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void map_rcba(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_port80_on_lpc(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable port 80 POST on LPC. The chipset does this by default,</span><br><span style="color: hsl(0, 100%, 40%);">- * but it doesn't appear to hurt anything. */</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gcs = RCBA32(GCS);</span><br><span style="color: hsl(0, 100%, 40%);">- gcs = gcs & ~0x4;</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(GCS) = gcs;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void set_spi_speed(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 fdod;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 ssfc;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Observe SPI Descriptor Component Section 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- SPIBAR32(FDOC) = 0x1000;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Extract the Write/Erase SPI Frequency from descriptor */</span><br><span style="color: hsl(0, 100%, 40%);">- fdod = SPIBAR32(FDOD);</span><br><span style="color: hsl(0, 100%, 40%);">- fdod >>= 24;</span><br><span style="color: hsl(0, 100%, 40%);">- fdod &= 7;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Software Sequence frequency to match */</span><br><span style="color: hsl(0, 100%, 40%);">- ssfc = SPIBAR8(SSFC + 2);</span><br><span style="color: hsl(0, 100%, 40%);">- ssfc &= ~7;</span><br><span style="color: hsl(0, 100%, 40%);">- ssfc |= fdod;</span><br><span style="color: hsl(0, 100%, 40%);">- SPIBAR8(SSFC + 2) = ssfc;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_early_southbridge_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- map_rcba();</span><br><span style="color: hsl(0, 100%, 40%);">- enable_spi_prefetch();</span><br><span style="color: hsl(0, 100%, 40%);">- enable_port80_on_lpc();</span><br><span style="color: hsl(0, 100%, 40%);">- set_spi_speed();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable upper 128bytes of CMOS */</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA32(RC) = (1 << 2);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pch_enable_lpc();</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_config_superio();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30316">change 30316</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I66387ae13939df41abdba9fb0015774e363100e4 </div>
<div style="display:none"> Gerrit-Change-Number: 30316 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>