[coreboot-gerrit] Change in ...coreboot[master]: [WIP]sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30315


Change subject: [WIP]sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock
......................................................................

[WIP]sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock

This allows for serial console during the bootblock.

TODO: move out the SIO to another file as linking romstage.c in
the bootblock is just confusing.

Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/asrock/h81m-hds/Makefile.inc
M src/southbridge/intel/lynxpoint/Makefile.inc
M src/southbridge/intel/lynxpoint/bootblock_gcc.c
M src/southbridge/intel/lynxpoint/early_pch.c
4 files changed, 5 insertions(+), 5 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30315/1

diff --git a/src/mainboard/asrock/h81m-hds/Makefile.inc b/src/mainboard/asrock/h81m-hds/Makefile.inc
index 94bd1cfe..bf2a63e 100644
--- a/src/mainboard/asrock/h81m-hds/Makefile.inc
+++ b/src/mainboard/asrock/h81m-hds/Makefile.inc
@@ -15,3 +15,4 @@
 ##
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += romstage.c
\ No newline at end of file
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 2b2144c..5196c3c 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -47,6 +47,7 @@
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c pch.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c
 
+bootblock-y += early_pch.c
 romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c
 romstage-y += early_spi.c rcba.c pmutil.c
 
diff --git a/src/southbridge/intel/lynxpoint/bootblock_gcc.c b/src/southbridge/intel/lynxpoint/bootblock_gcc.c
index dd9e112..85ccc27 100644
--- a/src/southbridge/intel/lynxpoint/bootblock_gcc.c
+++ b/src/southbridge/intel/lynxpoint/bootblock_gcc.c
@@ -79,4 +79,7 @@
 
 	/* Enable upper 128bytes of CMOS */
 	RCBA32(RC) = (1 << 2);
+
+	pch_enable_lpc();
+	mainboard_config_superio();
 }
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 134f9d7..fef788a 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -133,8 +133,6 @@
 {
 	int wake_from_s3;
 
-	pch_enable_lpc();
-
 	pch_enable_bars();
 
 #if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
@@ -142,9 +140,6 @@
 #else
 	setup_pch_gpios(gpio_map);
 #endif
-
-	mainboard_config_superio();
-
 	pch_generic_setup();
 
 	/* Enable SMBus for reading SPDs. */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4
Gerrit-Change-Number: 30315
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-MessageType: newchange
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