<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30315">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock<br><br>This allows for serial console during the bootblock.<br><br>TODO: move out the SIO to another file as linking romstage.c in<br>the bootblock is just confusing.<br><br>Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/asrock/h81m-hds/Makefile.inc<br>M src/southbridge/intel/lynxpoint/Makefile.inc<br>M src/southbridge/intel/lynxpoint/bootblock_gcc.c<br>M src/southbridge/intel/lynxpoint/early_pch.c<br>4 files changed, 5 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30315/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/asrock/h81m-hds/Makefile.inc b/src/mainboard/asrock/h81m-hds/Makefile.inc</span><br><span>index 94bd1cfe..bf2a63e 100644</span><br><span>--- a/src/mainboard/asrock/h81m-hds/Makefile.inc</span><br><span>+++ b/src/mainboard/asrock/h81m-hds/Makefile.inc</span><br><span>@@ -15,3 +15,4 @@</span><br><span> ##</span><br><span> </span><br><span> ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += romstage.c</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc</span><br><span>index 2b2144c..5196c3c 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/Makefile.inc</span><br><span>+++ b/src/southbridge/intel/lynxpoint/Makefile.inc</span><br><span>@@ -47,6 +47,7 @@</span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c pch.c</span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += early_pch.c</span><br><span> romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c</span><br><span> romstage-y += early_spi.c rcba.c pmutil.c</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/lynxpoint/bootblock_gcc.c b/src/southbridge/intel/lynxpoint/bootblock_gcc.c</span><br><span>index dd9e112..85ccc27 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/bootblock_gcc.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/bootblock_gcc.c</span><br><span>@@ -79,4 +79,7 @@</span><br><span> </span><br><span>         /* Enable upper 128bytes of CMOS */</span><br><span>  RCBA32(RC) = (1 << 2);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+        pch_enable_lpc();</span><br><span style="color: hsl(120, 100%, 40%);">+     mainboard_config_superio();</span><br><span> }</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c</span><br><span>index 134f9d7..fef788a 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/early_pch.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/early_pch.c</span><br><span>@@ -133,8 +133,6 @@</span><br><span> {</span><br><span>         int wake_from_s3;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-   pch_enable_lpc();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span>    pch_enable_bars();</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)</span><br><span>@@ -142,9 +140,6 @@</span><br><span> #else</span><br><span>   setup_pch_gpios(gpio_map);</span><br><span> #endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-    mainboard_config_superio();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span>  pch_generic_setup();</span><br><span> </span><br><span>     /* Enable SMBus for reading SPDs. */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30315">change 30315</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30315"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4 </div>
<div style="display:none"> Gerrit-Change-Number: 30315 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>