[coreboot-gerrit] Change in ...coreboot[master]: mb/ocp/wedge100s/romstage: Workaround broken platform state

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30290 )

Change subject: mb/ocp/wedge100s/romstage: Workaround broken platform state
......................................................................

mb/ocp/wedge100s/romstage: Workaround broken platform state

Sometimes the platform boots in an invalid state, that will cause
FSP-M to fail. As a board_reset() doesn't fix it, issue an full_reset()
as soon as the IA32_FEATURE_CONTROL MSR is locked at beging of romstage.

Tested on wedge100s. After full reset the system behaves as normal.

Change-Id: I1a382b8fb650311b0c24b48e0986d22edfa2d261
Signed-off-by: Patrick Rudolph <patrick.rudolph at 9elements.com>
Reviewed-on: https://review.coreboot.org/c/30290
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Nico Huber <nico.h at gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
---
M src/mainboard/ocp/wedge100s/romstage.c
1 file changed, 19 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Philipp Deppenwiese: Looks good to me, approved



diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c
index cf52c01..1d77036 100644
--- a/src/mainboard/ocp/wedge100s/romstage.c
+++ b/src/mainboard/ocp/wedge100s/romstage.c
@@ -17,6 +17,9 @@
 #include <stddef.h>
 #include <soc/romstage.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>
+#include <cpu/x86/msr.h>
+#include <cf9_reset.h>
+#include <console/console.h>
 
 /**
  * /brief mainboard call for setup that needs to be done before fsp init
@@ -24,7 +27,22 @@
  */
 void early_mainboard_romstage_entry(void)
 {
-
+	/*
+	 * Sometimes the system boots in an invalid state, where random values
+	 * have been written to MSRs and then the MSRs are locked.
+	 * Seems to always happen on warm reset.
+	 *
+	 * Power cycling or a board_reset() isn't sufficient in this case, so
+	 * issue a full_reset() to "fix" this issue.
+	 *
+	 * It seems to be a deficiency in the reset logic, as other
+	 * FSP broadwell DE boards are not affected.
+	 */
+	msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
+	if (msr.lo & 1) {
+		printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
+		full_reset();
+	}
 }
 
 /**

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1a382b8fb650311b0c24b48e0986d22edfa2d261
Gerrit-Change-Number: 30290
Gerrit-PatchSet: 4
Gerrit-Owner: Patrick Rudolph <patrick.rudolph at 9elements.com>
Gerrit-Reviewer: Andrea Barberio <insomniac at slackware.it>
Gerrit-Reviewer: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: David Hendricks <david.hendricks at gmail.com>
Gerrit-Reviewer: Jay Talbott <JayTalbott at sysproconsulting.com>
Gerrit-Reviewer: Nico Huber <nico.h at gmx.de>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph at 9elements.com>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh at siemens.com>
Gerrit-Reviewer: York Yang <york.yang at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-MessageType: merged
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