<p>Philipp Deppenwiese <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30290">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
Philipp Deppenwiese: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/ocp/wedge100s/romstage: Workaround broken platform state<br><br>Sometimes the platform boots in an invalid state, that will cause<br>FSP-M to fail. As a board_reset() doesn't fix it, issue an full_reset()<br>as soon as the IA32_FEATURE_CONTROL MSR is locked at beging of romstage.<br><br>Tested on wedge100s. After full reset the system behaves as normal.<br><br>Change-Id: I1a382b8fb650311b0c24b48e0986d22edfa2d261<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>Reviewed-on: https://review.coreboot.org/c/30290<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Nico Huber <nico.h@gmx.de><br>Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com><br>---<br>M src/mainboard/ocp/wedge100s/romstage.c<br>1 file changed, 19 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c</span><br><span>index cf52c01..1d77036 100644</span><br><span>--- a/src/mainboard/ocp/wedge100s/romstage.c</span><br><span>+++ b/src/mainboard/ocp/wedge100s/romstage.c</span><br><span>@@ -17,6 +17,9 @@</span><br><span> #include <stddef.h></span><br><span> #include <soc/romstage.h></span><br><span> #include <drivers/intel/fsp1_0/fsp_util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cf9_reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span> </span><br><span> /**</span><br><span> * /brief mainboard call for setup that needs to be done before fsp init</span><br><span>@@ -24,7 +27,22 @@</span><br><span> */</span><br><span> void early_mainboard_romstage_entry(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Sometimes the system boots in an invalid state, where random values</span><br><span style="color: hsl(120, 100%, 40%);">+ * have been written to MSRs and then the MSRs are locked.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Seems to always happen on warm reset.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Power cycling or a board_reset() isn't sufficient in this case, so</span><br><span style="color: hsl(120, 100%, 40%);">+ * issue a full_reset() to "fix" this issue.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * It seems to be a deficiency in the reset logic, as other</span><br><span style="color: hsl(120, 100%, 40%);">+ * FSP broadwell DE boards are not affected.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t msr = rdmsr(IA32_FEATURE_CONTROL);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (msr.lo & 1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ full_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span> </span><br><span> /**</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30290">change 30290</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30290"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I1a382b8fb650311b0c24b48e0986d22edfa2d261 </div>
<div style="display:none"> Gerrit-Change-Number: 30290 </div>
<div style="display:none"> Gerrit-PatchSet: 4 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>
<div style="display:none"> Gerrit-Reviewer: Andrea Barberio <insomniac@slackware.it> </div>
<div style="display:none"> Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: David Hendricks <david.hendricks@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Jay Talbott <JayTalbott@sysproconsulting.com> </div>
<div style="display:none"> Gerrit-Reviewer: Nico Huber <nico.h@gmx.de> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph@9elements.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Werner Zeh <werner.zeh@siemens.com> </div>
<div style="display:none"> Gerrit-Reviewer: York Yang <york.yang@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>