[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: SATA and DMI power optimize

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30211 )

Change subject: soc/intel/cannonlake: SATA and DMI power optimize
......................................................................

soc/intel/cannonlake: SATA and DMI power optimize

Expose the FSP interface to enable SATA and PCH side DMI power optimize
options. Actual step executed in FSP, step defined in cannonlake pch
BIOS spec(CDI# 570374).

Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
Change-Id: Ic0c589bb21e56800090bc0c75a0256a0409efc78
Reviewed-on: https://review.coreboot.org/c/30211
Reviewed-by: Patrick Georgi <pgeorgi at google.com>
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 10 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved



diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 3502178..3a723d2 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -296,6 +296,12 @@
 	uint8_t SlowSlewRateForGt;
 	uint8_t SlowSlewRateForSa;
 	uint8_t SlowSlewRateForFivr;
+
+	/* DMI Power Optimizer */
+	uint8_t dmipwroptimize;
+
+	/* SATA Power Optimizer */
+	uint8_t satapwroptimize;
 };
 
 typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index a9326a4..78b27e9 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -221,6 +221,10 @@
 	params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt;
 	params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa;
 	params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr;
+
+	/* Power Optimizer */
+	params->PchPwrOptEnable = config->dmipwroptimize;
+	params->SataPwrOptEnable = config->satapwroptimize;
 }
 
 /* Mainboard GPIO Configuration */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic0c589bb21e56800090bc0c75a0256a0409efc78
Gerrit-Change-Number: 30211
Gerrit-PatchSet: 3
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-MessageType: merged
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