<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30211">View Change</a></p><div style="white-space:pre-wrap">Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved

</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: SATA and DMI power optimize<br><br>Expose the FSP interface to enable SATA and PCH side DMI power optimize<br>options. Actual step executed in FSP, step defined in cannonlake pch<br>BIOS spec(CDI# 570374).<br><br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>Change-Id: Ic0c589bb21e56800090bc0c75a0256a0409efc78<br>Reviewed-on: https://review.coreboot.org/c/30211<br>Reviewed-by: Patrick Georgi <pgeorgi@google.com><br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>---<br>M src/soc/intel/cannonlake/chip.h<br>M src/soc/intel/cannonlake/fsp_params.c<br>2 files changed, 10 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h</span><br><span>index 3502178..3a723d2 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.h</span><br><span>+++ b/src/soc/intel/cannonlake/chip.h</span><br><span>@@ -296,6 +296,12 @@</span><br><span>   uint8_t SlowSlewRateForGt;</span><br><span>   uint8_t SlowSlewRateForSa;</span><br><span>   uint8_t SlowSlewRateForFivr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+        /* DMI Power Optimizer */</span><br><span style="color: hsl(120, 100%, 40%);">+     uint8_t dmipwroptimize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+     /* SATA Power Optimizer */</span><br><span style="color: hsl(120, 100%, 40%);">+    uint8_t satapwroptimize;</span><br><span> };</span><br><span> </span><br><span> typedef struct soc_intel_cannonlake_config config_t;</span><br><span>diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c</span><br><span>index a9326a4..78b27e9 100644</span><br><span>--- a/src/soc/intel/cannonlake/fsp_params.c</span><br><span>+++ b/src/soc/intel/cannonlake/fsp_params.c</span><br><span>@@ -221,6 +221,10 @@</span><br><span>   params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt;</span><br><span>         params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa;</span><br><span>         params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+    /* Power Optimizer */</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchPwrOptEnable = config->dmipwroptimize;</span><br><span style="color: hsl(120, 100%, 40%);">+       params->SataPwrOptEnable = config->satapwroptimize;</span><br><span> }</span><br><span> </span><br><span> /* Mainboard GPIO Configuration */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30211">change 30211</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30211"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ic0c589bb21e56800090bc0c75a0256a0409efc78 </div>
<div style="display:none"> Gerrit-Change-Number: 30211 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Bora Guvendik <bora.guvendik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>