[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Declare SATA Mode clear

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30093 )

Change subject: soc/intel/cannonlake: Declare SATA Mode clear
......................................................................

soc/intel/cannonlake: Declare SATA Mode clear

FSP support two SATA modes as AHCI mode (0) and RAID mode (1), make it
more clear in header file.

Change-Id: I1edcadc0048df839da145260b60f9f7720d981fe
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
Reviewed-on: https://review.coreboot.org/c/30093
Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
Reviewed-by: Patrick Rudolph <siro at das-labor.org>
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
---
M src/soc/intel/cannonlake/chip.h
1 file changed, 4 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Duncan Laurie: Looks good to me, approved
  Patrick Rudolph: Looks good to me, approved



diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 8eaf02b..962748f 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -124,7 +124,10 @@
 	uint16_t usb3_wake_enable_bitmap;
 
 	/* SATA related */
-	uint8_t SataMode;
+	enum {
+		Sata_AHCI,
+		Sata_RAID,
+	} SataMode;
 	uint8_t SataSalpSupport;
 	uint8_t SataPortsEnable[8];
 	uint8_t SataPortsDevSlp[8];

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1edcadc0048df839da145260b60f9f7720d981fe
Gerrit-Change-Number: 30093
Gerrit-PatchSet: 6
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-MessageType: merged
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