[coreboot-gerrit] Change in ...coreboot[master]: southbridge: Remove useless include <device/pci_ids.h>
Patrick Georgi (Code Review)
gerrit at coreboot.org
Wed Dec 19 06:23:06 CET 2018
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30120 )
Change subject: southbridge: Remove useless include <device/pci_ids.h>
......................................................................
southbridge: Remove useless include <device/pci_ids.h>
Change-Id: Ia640131479d4221ccd84613033f28de3932b8bff
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
Reviewed-on: https://review.coreboot.org/c/30120
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh at siemens.com>
---
M src/southbridge/amd/agesa/hudson/bootblock.c
M src/southbridge/amd/agesa/hudson/hudson.h
M src/southbridge/amd/amd8111/early_ctrl.c
M src/southbridge/amd/pi/hudson/hudson.h
M src/southbridge/amd/rs780/cmn.c
M src/southbridge/amd/rs780/pcie.c
M src/southbridge/amd/rs780/rs780.c
M src/southbridge/amd/rs780/rs780.h
M src/southbridge/amd/sb700/bootblock.c
M src/southbridge/amd/sb700/sb700.h
M src/southbridge/amd/sb800/bootblock.c
M src/southbridge/amd/sb800/sb800.h
M src/southbridge/amd/sr5650/pcie.c
M src/southbridge/amd/sr5650/sr5650.h
M src/southbridge/intel/bd82x6x/early_me.c
M src/southbridge/intel/bd82x6x/early_me_mrc.c
M src/southbridge/intel/bd82x6x/early_smbus.c
M src/southbridge/intel/bd82x6x/early_spi.c
M src/southbridge/intel/bd82x6x/early_usb.c
M src/southbridge/intel/bd82x6x/early_usb_mrc.c
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/fsp_rangeley/early_smbus.c
M src/southbridge/intel/fsp_rangeley/early_spi.c
M src/southbridge/intel/fsp_rangeley/early_usb.c
M src/southbridge/intel/i82371eb/acpi_tables.c
M src/southbridge/intel/i82801dx/i82801dx.c
M src/southbridge/intel/i82801gx/early_smbus.c
M src/southbridge/intel/i82801ix/early_smbus.c
M src/southbridge/intel/i82801jx/early_smbus.c
M src/southbridge/intel/ibexpeak/early_smbus.c
M src/southbridge/intel/ibexpeak/madt.c
M src/southbridge/intel/lynxpoint/early_me.c
M src/southbridge/intel/lynxpoint/early_smbus.c
M src/southbridge/intel/lynxpoint/early_spi.c
M src/southbridge/intel/lynxpoint/early_usb.c
M src/southbridge/ti/pci7420/cardbus.c
M src/southbridge/ti/pci7420/firewire.c
M src/southbridge/ti/pcixx12/pcixx12.c
38 files changed, 2 insertions(+), 38 deletions(-)
Approvals:
build bot (Jenkins): Verified
Werner Zeh: Looks good to me, approved
diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c
index 32b1298..bb6a54b 100644
--- a/src/southbridge/amd/agesa/hudson/bootblock.c
+++ b/src/southbridge/amd/agesa/hudson/bootblock.c
@@ -15,7 +15,6 @@
#include <stdint.h>
#include <arch/io.h>
-#include <device/pci_ids.h>
/*
* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h
index 165d33f..bd49e8f 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.h
+++ b/src/southbridge/amd/agesa/hudson/hudson.h
@@ -17,7 +17,6 @@
#ifndef HUDSON_H
#define HUDSON_H
-#include <device/pci_ids.h>
#include <device/device.h>
#include "chip.h"
diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c
index ce29bf1..1754d23 100644
--- a/src/southbridge/amd/amd8111/early_ctrl.c
+++ b/src/southbridge/amd/amd8111/early_ctrl.c
@@ -13,9 +13,10 @@
* GNU General Public License for more details.
*/
-#include "amd8111.h"
+#include <device/pci_ids.h>
#include <reset.h>
#include <southbridge/amd/common/reset.h>
+#include "amd8111.h"
unsigned get_sbdn(unsigned bus)
{
diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index 922c608..27ae4ed 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -18,7 +18,6 @@
#define HUDSON_H
#include <types.h>
-#include <device/pci_ids.h>
#include <device/device.h>
#include "chip.h"
diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c
index 23cd877..16270d6 100644
--- a/src/southbridge/amd/rs780/cmn.c
+++ b/src/southbridge/amd/rs780/cmn.c
@@ -18,7 +18,6 @@
#include <arch/cpu.h>
#include <device/device.h>
#include <device/pci.h>
-#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c
index adf5401..437a62a 100644
--- a/src/southbridge/amd/rs780/pcie.c
+++ b/src/southbridge/amd/rs780/pcie.c
@@ -16,7 +16,6 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <delay.h>
#include "rs780.h"
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index 3c9393d..36b37cc 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -18,7 +18,6 @@
#include <arch/acpi.h>
#include <device/device.h>
#include <device/pci.h>
-#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h
index e96608e..354555f 100644
--- a/src/southbridge/amd/rs780/rs780.h
+++ b/src/southbridge/amd/rs780/rs780.h
@@ -18,7 +18,6 @@
#include <rules.h>
#include <stdint.h>
-#include <device/pci_ids.h>
#include "chip.h"
#include "rev.h"
diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index e77db5c..364fa01 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -16,7 +16,6 @@
#include <stdint.h>
#include <arch/io.h>
-#include <device/pci_ids.h>
#define IO_MEM_PORT_DECODE_ENABLE_5 0x48
#define IO_MEM_PORT_DECODE_ENABLE_6 0x4a
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index 73c0b37..0b638f6 100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -17,7 +17,6 @@
#ifndef SB700_H
#define SB700_H
-#include <device/pci_ids.h>
#include "chip.h"
/* Power management index/data registers */
diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c
index e95d4e9..b08d477 100644
--- a/src/southbridge/amd/sb800/bootblock.c
+++ b/src/southbridge/amd/sb800/bootblock.c
@@ -15,7 +15,6 @@
#include <stdint.h>
#include <arch/io.h>
-#include <device/pci_ids.h>
/*
* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h
index a65c68a9..3715a3a 100644
--- a/src/southbridge/amd/sb800/sb800.h
+++ b/src/southbridge/amd/sb800/sb800.h
@@ -17,7 +17,6 @@
#ifndef SB800_H
#define SB800_H
-#include <device/pci_ids.h>
#include "chip.h"
/* Power management index/data registers */
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
index 159f3e4..f2fd539 100644
--- a/src/southbridge/amd/sr5650/pcie.c
+++ b/src/southbridge/amd/sr5650/pcie.c
@@ -17,7 +17,6 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <delay.h>
#include "sr5650.h"
diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h
index 2e6b728..06a4279 100644
--- a/src/southbridge/amd/sr5650/sr5650.h
+++ b/src/southbridge/amd/sr5650/sr5650.h
@@ -19,7 +19,6 @@
#include <stdint.h>
#include <arch/acpi.h>
-#include <device/pci_ids.h>
#include "chip.h"
#include "rev.h"
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c
index bda139b..ee149d0 100644
--- a/src/southbridge/intel/bd82x6x/early_me.c
+++ b/src/southbridge/intel/bd82x6x/early_me.c
@@ -17,7 +17,6 @@
#include <arch/io.h>
#include <console/console.h>
#include <delay.h>
-#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <halt.h>
#include <string.h>
diff --git a/src/southbridge/intel/bd82x6x/early_me_mrc.c b/src/southbridge/intel/bd82x6x/early_me_mrc.c
index a6562c7..ed27573 100644
--- a/src/southbridge/intel/bd82x6x/early_me_mrc.c
+++ b/src/southbridge/intel/bd82x6x/early_me_mrc.c
@@ -17,7 +17,6 @@
#include <arch/io.h>
#include <console/console.h>
#include <delay.h>
-#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <halt.h>
#include <string.h>
diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c
index 4c67aea..3cd98ac 100644
--- a/src/southbridge/intel/bd82x6x/early_smbus.c
+++ b/src/southbridge/intel/bd82x6x/early_smbus.c
@@ -16,7 +16,6 @@
#include <arch/io.h>
#include <console/console.h>
-#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <southbridge/intel/common/smbus.h>
#include "pch.h"
diff --git a/src/southbridge/intel/bd82x6x/early_spi.c b/src/southbridge/intel/bd82x6x/early_spi.c
index 1400837..e3f07ad 100644
--- a/src/southbridge/intel/bd82x6x/early_spi.c
+++ b/src/southbridge/intel/bd82x6x/early_spi.c
@@ -16,7 +16,6 @@
#include <arch/io.h>
#include <console/console.h>
-#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <delay.h>
#include "pch.h"
diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c
index 1044953..c34b3ec 100644
--- a/src/southbridge/intel/bd82x6x/early_usb.c
+++ b/src/southbridge/intel/bd82x6x/early_usb.c
@@ -15,7 +15,6 @@
*/
#include <arch/io.h>
-#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include "pch.h"
diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c
index 8006d95..e4fadad 100644
--- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c
+++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c
@@ -15,7 +15,6 @@
*/
#include <arch/io.h>
-#include <device/pci_ids.h>
#include <device/pci_def.h>
#include "pch.h"
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index fe3bf2a..3ca0d6c 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -25,7 +25,6 @@
#include <delay.h>
#include <arch/io.h>
#include <console/console.h>
-#include <device/pci_ids.h>
#include <device/pci.h>
#include <spi_flash.h>
diff --git a/src/southbridge/intel/fsp_rangeley/early_smbus.c b/src/southbridge/intel/fsp_rangeley/early_smbus.c
index 84b750e..9b47837 100644
--- a/src/southbridge/intel/fsp_rangeley/early_smbus.c
+++ b/src/southbridge/intel/fsp_rangeley/early_smbus.c
@@ -16,7 +16,6 @@
#include <arch/io.h>
#include <console/console.h>
-#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <southbridge/intel/common/smbus.h>
#include "soc.h"
diff --git a/src/southbridge/intel/fsp_rangeley/early_spi.c b/src/southbridge/intel/fsp_rangeley/early_spi.c
index dbf6003..3c4f2d7 100644
--- a/src/southbridge/intel/fsp_rangeley/early_spi.c
+++ b/src/southbridge/intel/fsp_rangeley/early_spi.c
@@ -16,7 +16,6 @@
#include <arch/io.h>
#include <console/console.h>
-#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <delay.h>
#include "soc.h"
diff --git a/src/southbridge/intel/fsp_rangeley/early_usb.c b/src/southbridge/intel/fsp_rangeley/early_usb.c
index 3bb8dab..0bcd09d 100644
--- a/src/southbridge/intel/fsp_rangeley/early_usb.c
+++ b/src/southbridge/intel/fsp_rangeley/early_usb.c
@@ -15,7 +15,6 @@
*/
#include <arch/io.h>
-#include <device/pci_ids.h>
#include <device/pci_def.h>
#include "soc.h"
diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c
index 9a720e2..7c6d3b4 100644
--- a/src/southbridge/intel/i82371eb/acpi_tables.c
+++ b/src/southbridge/intel/i82371eb/acpi_tables.c
@@ -21,7 +21,6 @@
#include <arch/acpigen.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
-#include <device/pci_ids.h>
#include "i82371eb.h"
static int determine_total_number_of_cores(void)
diff --git a/src/southbridge/intel/i82801dx/i82801dx.c b/src/southbridge/intel/i82801dx/i82801dx.c
index fc38207..8db591c 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.c
+++ b/src/southbridge/intel/i82801dx/i82801dx.c
@@ -16,7 +16,6 @@
#include <device/device.h>
#include <device/pci.h>
-#include <device/pci_ids.h>
#include "i82801dx.h"
void i82801dx_enable(struct device *dev)
diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c
index bb5caf5..698458b 100644
--- a/src/southbridge/intel/i82801gx/early_smbus.c
+++ b/src/southbridge/intel/i82801gx/early_smbus.c
@@ -16,7 +16,6 @@
#include <arch/io.h>
#include <console/console.h>
-#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <southbridge/intel/common/smbus.h>
#include "i82801gx.h"
diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c
index 0e4195c..0dda0c8 100644
--- a/src/southbridge/intel/i82801ix/early_smbus.c
+++ b/src/southbridge/intel/i82801ix/early_smbus.c
@@ -17,7 +17,6 @@
#include <arch/io.h>
#include <console/console.h>
-#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <southbridge/intel/common/smbus.h>
#include "i82801ix.h"
diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c
index 16932e0..bd68955 100644
--- a/src/southbridge/intel/i82801jx/early_smbus.c
+++ b/src/southbridge/intel/i82801jx/early_smbus.c
@@ -17,7 +17,6 @@
#include <arch/io.h>
#include <console/console.h>
-#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <southbridge/intel/common/smbus.h>
#include "i82801jx.h"
diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c
index b7823eb..8760a82 100644
--- a/src/southbridge/intel/ibexpeak/early_smbus.c
+++ b/src/southbridge/intel/ibexpeak/early_smbus.c
@@ -16,7 +16,6 @@
#include <arch/io.h>
#include <console/console.h>
-#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <southbridge/intel/common/smbus.h>
#include "pch.h"
diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c
index e02cd88..585df93 100644
--- a/src/southbridge/intel/ibexpeak/madt.c
+++ b/src/southbridge/intel/ibexpeak/madt.c
@@ -23,7 +23,6 @@
#include <arch/smp/mpspec.h>
#include <device/device.h>
#include <device/pci.h>
-#include <device/pci_ids.h>
unsigned long acpi_fill_madt(unsigned long current)
{
diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c
index 674534f..e02a16c 100644
--- a/src/southbridge/intel/lynxpoint/early_me.c
+++ b/src/southbridge/intel/lynxpoint/early_me.c
@@ -17,7 +17,6 @@
#include <arch/io.h>
#include <console/console.h>
#include <delay.h>
-#include <device/pci_ids.h>
#include <halt.h>
#include <string.h>
#include "me.h"
diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c
index 4c67aea..3cd98ac 100644
--- a/src/southbridge/intel/lynxpoint/early_smbus.c
+++ b/src/southbridge/intel/lynxpoint/early_smbus.c
@@ -16,7 +16,6 @@
#include <arch/io.h>
#include <console/console.h>
-#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <southbridge/intel/common/smbus.h>
#include "pch.h"
diff --git a/src/southbridge/intel/lynxpoint/early_spi.c b/src/southbridge/intel/lynxpoint/early_spi.c
index 1400837..e3f07ad 100644
--- a/src/southbridge/intel/lynxpoint/early_spi.c
+++ b/src/southbridge/intel/lynxpoint/early_spi.c
@@ -16,7 +16,6 @@
#include <arch/io.h>
#include <console/console.h>
-#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <delay.h>
#include "pch.h"
diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c
index 60ab09d..4b44716 100644
--- a/src/southbridge/intel/lynxpoint/early_usb.c
+++ b/src/southbridge/intel/lynxpoint/early_usb.c
@@ -15,7 +15,6 @@
*/
#include <arch/io.h>
-#include <device/pci_ids.h>
#include <device/pci_def.h>
#include "pch.h"
diff --git a/src/southbridge/ti/pci7420/cardbus.c b/src/southbridge/ti/pci7420/cardbus.c
index 910b0c8..3c88529 100644
--- a/src/southbridge/ti/pci7420/cardbus.c
+++ b/src/southbridge/ti/pci7420/cardbus.c
@@ -18,7 +18,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
-#include <device/pci_ids.h>
#include <console/console.h>
#include <device/cardbus.h>
#include "pci7420.h"
diff --git a/src/southbridge/ti/pci7420/firewire.c b/src/southbridge/ti/pci7420/firewire.c
index e42b6a6..1379d59 100644
--- a/src/southbridge/ti/pci7420/firewire.c
+++ b/src/southbridge/ti/pci7420/firewire.c
@@ -18,7 +18,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
-#include <device/pci_ids.h>
#include <console/console.h>
#include <device/cardbus.h>
#include "pci7420.h"
diff --git a/src/southbridge/ti/pcixx12/pcixx12.c b/src/southbridge/ti/pcixx12/pcixx12.c
index ab7231e..6385ba9 100644
--- a/src/southbridge/ti/pcixx12/pcixx12.c
+++ b/src/southbridge/ti/pcixx12/pcixx12.c
@@ -17,7 +17,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
-#include <device/pci_ids.h>
#include <console/console.h>
#include <device/cardbus.h>
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ia640131479d4221ccd84613033f28de3932b8bff
Gerrit-Change-Number: 30120
Gerrit-PatchSet: 5
Gerrit-Owner: HAOUAS Elyes <ehaouas at noos.fr>
Gerrit-Reviewer: Alexander Couzens <lynxis at fe80.eu>
Gerrit-Reviewer: Damien Zammit <damien at zamaudio.com>
Gerrit-Reviewer: David Guckian <david.guckian at intel.com>
Gerrit-Reviewer: HAOUAS Elyes <ehaouas at noos.fr>
Gerrit-Reviewer: Huang Jin <huang.jin at intel.com>
Gerrit-Reviewer: Michał Żygowski <michal.zygowski at 3mdeb.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
Gerrit-Reviewer: Piotr Król <piotr.krol at 3mdeb.com>
Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio at intel.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh at siemens.com>
Gerrit-Reviewer: York Yang <york.yang at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-MessageType: merged
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