<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30120">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Werner Zeh: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">southbridge: Remove useless include <device/pci_ids.h><br><br>Change-Id: Ia640131479d4221ccd84613033f28de3932b8bff<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>Reviewed-on: https://review.coreboot.org/c/30120<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Werner Zeh <werner.zeh@siemens.com><br>---<br>M src/southbridge/amd/agesa/hudson/bootblock.c<br>M src/southbridge/amd/agesa/hudson/hudson.h<br>M src/southbridge/amd/amd8111/early_ctrl.c<br>M src/southbridge/amd/pi/hudson/hudson.h<br>M src/southbridge/amd/rs780/cmn.c<br>M src/southbridge/amd/rs780/pcie.c<br>M src/southbridge/amd/rs780/rs780.c<br>M src/southbridge/amd/rs780/rs780.h<br>M src/southbridge/amd/sb700/bootblock.c<br>M src/southbridge/amd/sb700/sb700.h<br>M src/southbridge/amd/sb800/bootblock.c<br>M src/southbridge/amd/sb800/sb800.h<br>M src/southbridge/amd/sr5650/pcie.c<br>M src/southbridge/amd/sr5650/sr5650.h<br>M src/southbridge/intel/bd82x6x/early_me.c<br>M src/southbridge/intel/bd82x6x/early_me_mrc.c<br>M src/southbridge/intel/bd82x6x/early_smbus.c<br>M src/southbridge/intel/bd82x6x/early_spi.c<br>M src/southbridge/intel/bd82x6x/early_usb.c<br>M src/southbridge/intel/bd82x6x/early_usb_mrc.c<br>M src/southbridge/intel/common/spi.c<br>M src/southbridge/intel/fsp_rangeley/early_smbus.c<br>M src/southbridge/intel/fsp_rangeley/early_spi.c<br>M src/southbridge/intel/fsp_rangeley/early_usb.c<br>M src/southbridge/intel/i82371eb/acpi_tables.c<br>M src/southbridge/intel/i82801dx/i82801dx.c<br>M src/southbridge/intel/i82801gx/early_smbus.c<br>M src/southbridge/intel/i82801ix/early_smbus.c<br>M src/southbridge/intel/i82801jx/early_smbus.c<br>M src/southbridge/intel/ibexpeak/early_smbus.c<br>M src/southbridge/intel/ibexpeak/madt.c<br>M src/southbridge/intel/lynxpoint/early_me.c<br>M src/southbridge/intel/lynxpoint/early_smbus.c<br>M src/southbridge/intel/lynxpoint/early_spi.c<br>M src/southbridge/intel/lynxpoint/early_usb.c<br>M src/southbridge/ti/pci7420/cardbus.c<br>M src/southbridge/ti/pci7420/firewire.c<br>M src/southbridge/ti/pcixx12/pcixx12.c<br>38 files changed, 2 insertions(+), 38 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c</span><br><span>index 32b1298..bb6a54b 100644</span><br><span>--- a/src/southbridge/amd/agesa/hudson/bootblock.c</span><br><span>+++ b/src/southbridge/amd/agesa/hudson/bootblock.c</span><br><span>@@ -15,7 +15,6 @@</span><br><span> </span><br><span> #include <stdint.h></span><br><span> #include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> </span><br><span> /*</span><br><span> * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.</span><br><span>diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h</span><br><span>index 165d33f..bd49e8f 100644</span><br><span>--- a/src/southbridge/amd/agesa/hudson/hudson.h</span><br><span>+++ b/src/southbridge/amd/agesa/hudson/hudson.h</span><br><span>@@ -17,7 +17,6 @@</span><br><span> #ifndef HUDSON_H</span><br><span> #define HUDSON_H</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/device.h></span><br><span> #include "chip.h"</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c</span><br><span>index ce29bf1..1754d23 100644</span><br><span>--- a/src/southbridge/amd/amd8111/early_ctrl.c</span><br><span>+++ b/src/southbridge/amd/amd8111/early_ctrl.c</span><br><span>@@ -13,9 +13,10 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include "amd8111.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span> #include <reset.h></span><br><span> #include <southbridge/amd/common/reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "amd8111.h"</span><br><span> </span><br><span> unsigned get_sbdn(unsigned bus)</span><br><span> {</span><br><span>diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h</span><br><span>index 922c608..27ae4ed 100644</span><br><span>--- a/src/southbridge/amd/pi/hudson/hudson.h</span><br><span>+++ b/src/southbridge/amd/pi/hudson/hudson.h</span><br><span>@@ -18,7 +18,6 @@</span><br><span> #define HUDSON_H</span><br><span> </span><br><span> #include <types.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/device.h></span><br><span> #include "chip.h"</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c</span><br><span>index 23cd877..16270d6 100644</span><br><span>--- a/src/southbridge/amd/rs780/cmn.c</span><br><span>+++ b/src/southbridge/amd/rs780/cmn.c</span><br><span>@@ -18,7 +18,6 @@</span><br><span> #include <arch/cpu.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_ops.h></span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span>diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c</span><br><span>index adf5401..437a62a 100644</span><br><span>--- a/src/southbridge/amd/rs780/pcie.c</span><br><span>+++ b/src/southbridge/amd/rs780/pcie.c</span><br><span>@@ -16,7 +16,6 @@</span><br><span> #include <console/console.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_ops.h></span><br><span> #include <delay.h></span><br><span> #include "rs780.h"</span><br><span>diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c</span><br><span>index 3c9393d..36b37cc 100644</span><br><span>--- a/src/southbridge/amd/rs780/rs780.c</span><br><span>+++ b/src/southbridge/amd/rs780/rs780.c</span><br><span>@@ -18,7 +18,6 @@</span><br><span> #include <arch/acpi.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_ops.h></span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span>diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h</span><br><span>index e96608e..354555f 100644</span><br><span>--- a/src/southbridge/amd/rs780/rs780.h</span><br><span>+++ b/src/southbridge/amd/rs780/rs780.h</span><br><span>@@ -18,7 +18,6 @@</span><br><span> </span><br><span> #include <rules.h></span><br><span> #include <stdint.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include "chip.h"</span><br><span> #include "rev.h"</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c</span><br><span>index e77db5c..364fa01 100644</span><br><span>--- a/src/southbridge/amd/sb700/bootblock.c</span><br><span>+++ b/src/southbridge/amd/sb700/bootblock.c</span><br><span>@@ -16,7 +16,6 @@</span><br><span> </span><br><span> #include <stdint.h></span><br><span> #include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> </span><br><span> #define IO_MEM_PORT_DECODE_ENABLE_5 0x48</span><br><span> #define IO_MEM_PORT_DECODE_ENABLE_6 0x4a</span><br><span>diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h</span><br><span>index 73c0b37..0b638f6 100644</span><br><span>--- a/src/southbridge/amd/sb700/sb700.h</span><br><span>+++ b/src/southbridge/amd/sb700/sb700.h</span><br><span>@@ -17,7 +17,6 @@</span><br><span> #ifndef SB700_H</span><br><span> #define SB700_H</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include "chip.h"</span><br><span> </span><br><span> /* Power management index/data registers */</span><br><span>diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c</span><br><span>index e95d4e9..b08d477 100644</span><br><span>--- a/src/southbridge/amd/sb800/bootblock.c</span><br><span>+++ b/src/southbridge/amd/sb800/bootblock.c</span><br><span>@@ -15,7 +15,6 @@</span><br><span> </span><br><span> #include <stdint.h></span><br><span> #include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> </span><br><span> /*</span><br><span> * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.</span><br><span>diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h</span><br><span>index a65c68a9..3715a3a 100644</span><br><span>--- a/src/southbridge/amd/sb800/sb800.h</span><br><span>+++ b/src/southbridge/amd/sb800/sb800.h</span><br><span>@@ -17,7 +17,6 @@</span><br><span> #ifndef SB800_H</span><br><span> #define SB800_H</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include "chip.h"</span><br><span> </span><br><span> /* Power management index/data registers */</span><br><span>diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c</span><br><span>index 159f3e4..f2fd539 100644</span><br><span>--- a/src/southbridge/amd/sr5650/pcie.c</span><br><span>+++ b/src/southbridge/amd/sr5650/pcie.c</span><br><span>@@ -17,7 +17,6 @@</span><br><span> #include <console/console.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_ops.h></span><br><span> #include <delay.h></span><br><span> #include "sr5650.h"</span><br><span>diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h</span><br><span>index 2e6b728..06a4279 100644</span><br><span>--- a/src/southbridge/amd/sr5650/sr5650.h</span><br><span>+++ b/src/southbridge/amd/sr5650/sr5650.h</span><br><span>@@ -19,7 +19,6 @@</span><br><span> </span><br><span> #include <stdint.h></span><br><span> #include <arch/acpi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include "chip.h"</span><br><span> #include "rev.h"</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c</span><br><span>index bda139b..ee149d0 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_me.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_me.c</span><br><span>@@ -17,7 +17,6 @@</span><br><span> #include <arch/io.h></span><br><span> #include <console/console.h></span><br><span> #include <delay.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <halt.h></span><br><span> #include <string.h></span><br><span>diff --git a/src/southbridge/intel/bd82x6x/early_me_mrc.c b/src/southbridge/intel/bd82x6x/early_me_mrc.c</span><br><span>index a6562c7..ed27573 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_me_mrc.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_me_mrc.c</span><br><span>@@ -17,7 +17,6 @@</span><br><span> #include <arch/io.h></span><br><span> #include <console/console.h></span><br><span> #include <delay.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <halt.h></span><br><span> #include <string.h></span><br><span>diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c</span><br><span>index 4c67aea..3cd98ac 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_smbus.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_smbus.c</span><br><span>@@ -16,7 +16,6 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <southbridge/intel/common/smbus.h></span><br><span> #include "pch.h"</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/early_spi.c b/src/southbridge/intel/bd82x6x/early_spi.c</span><br><span>index 1400837..e3f07ad 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_spi.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_spi.c</span><br><span>@@ -16,7 +16,6 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <delay.h></span><br><span> #include "pch.h"</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c</span><br><span>index 1044953..c34b3ec 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_usb.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_usb.c</span><br><span>@@ -15,7 +15,6 @@</span><br><span> */</span><br><span> </span><br><span> #include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> #include "pch.h"</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c</span><br><span>index 8006d95..e4fadad 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c</span><br><span>@@ -15,7 +15,6 @@</span><br><span> */</span><br><span> </span><br><span> #include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include "pch.h"</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c</span><br><span>index fe3bf2a..3ca0d6c 100644</span><br><span>--- a/src/southbridge/intel/common/spi.c</span><br><span>+++ b/src/southbridge/intel/common/spi.c</span><br><span>@@ -25,7 +25,6 @@</span><br><span> #include <delay.h></span><br><span> #include <arch/io.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci.h></span><br><span> #include <spi_flash.h></span><br><span> </span><br><span>diff --git a/src/southbridge/intel/fsp_rangeley/early_smbus.c b/src/southbridge/intel/fsp_rangeley/early_smbus.c</span><br><span>index 84b750e..9b47837 100644</span><br><span>--- a/src/southbridge/intel/fsp_rangeley/early_smbus.c</span><br><span>+++ b/src/southbridge/intel/fsp_rangeley/early_smbus.c</span><br><span>@@ -16,7 +16,6 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <southbridge/intel/common/smbus.h></span><br><span> #include "soc.h"</span><br><span>diff --git a/src/southbridge/intel/fsp_rangeley/early_spi.c b/src/southbridge/intel/fsp_rangeley/early_spi.c</span><br><span>index dbf6003..3c4f2d7 100644</span><br><span>--- a/src/southbridge/intel/fsp_rangeley/early_spi.c</span><br><span>+++ b/src/southbridge/intel/fsp_rangeley/early_spi.c</span><br><span>@@ -16,7 +16,6 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <delay.h></span><br><span> #include "soc.h"</span><br><span>diff --git a/src/southbridge/intel/fsp_rangeley/early_usb.c b/src/southbridge/intel/fsp_rangeley/early_usb.c</span><br><span>index 3bb8dab..0bcd09d 100644</span><br><span>--- a/src/southbridge/intel/fsp_rangeley/early_usb.c</span><br><span>+++ b/src/southbridge/intel/fsp_rangeley/early_usb.c</span><br><span>@@ -15,7 +15,6 @@</span><br><span> */</span><br><span> </span><br><span> #include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include "soc.h"</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c</span><br><span>index 9a720e2..7c6d3b4 100644</span><br><span>--- a/src/southbridge/intel/i82371eb/acpi_tables.c</span><br><span>+++ b/src/southbridge/intel/i82371eb/acpi_tables.c</span><br><span>@@ -21,7 +21,6 @@</span><br><span> #include <arch/acpigen.h></span><br><span> #include <arch/smp/mpspec.h></span><br><span> #include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include "i82371eb.h"</span><br><span> </span><br><span> static int determine_total_number_of_cores(void)</span><br><span>diff --git a/src/southbridge/intel/i82801dx/i82801dx.c b/src/southbridge/intel/i82801dx/i82801dx.c</span><br><span>index fc38207..8db591c 100644</span><br><span>--- a/src/southbridge/intel/i82801dx/i82801dx.c</span><br><span>+++ b/src/southbridge/intel/i82801dx/i82801dx.c</span><br><span>@@ -16,7 +16,6 @@</span><br><span> </span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include "i82801dx.h"</span><br><span> </span><br><span> void i82801dx_enable(struct device *dev)</span><br><span>diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c</span><br><span>index bb5caf5..698458b 100644</span><br><span>--- a/src/southbridge/intel/i82801gx/early_smbus.c</span><br><span>+++ b/src/southbridge/intel/i82801gx/early_smbus.c</span><br><span>@@ -16,7 +16,6 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <southbridge/intel/common/smbus.h></span><br><span> #include "i82801gx.h"</span><br><span>diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c</span><br><span>index 0e4195c..0dda0c8 100644</span><br><span>--- a/src/southbridge/intel/i82801ix/early_smbus.c</span><br><span>+++ b/src/southbridge/intel/i82801ix/early_smbus.c</span><br><span>@@ -17,7 +17,6 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <southbridge/intel/common/smbus.h></span><br><span> #include "i82801ix.h"</span><br><span>diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c</span><br><span>index 16932e0..bd68955 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/early_smbus.c</span><br><span>+++ b/src/southbridge/intel/i82801jx/early_smbus.c</span><br><span>@@ -17,7 +17,6 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <southbridge/intel/common/smbus.h></span><br><span> #include "i82801jx.h"</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c</span><br><span>index b7823eb..8760a82 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/early_smbus.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/early_smbus.c</span><br><span>@@ -16,7 +16,6 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <southbridge/intel/common/smbus.h></span><br><span> #include "pch.h"</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c</span><br><span>index e02cd88..585df93 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/madt.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/madt.c</span><br><span>@@ -23,7 +23,6 @@</span><br><span> #include <arch/smp/mpspec.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> </span><br><span> unsigned long acpi_fill_madt(unsigned long current)</span><br><span> {</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c</span><br><span>index 674534f..e02a16c 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/early_me.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/early_me.c</span><br><span>@@ -17,7 +17,6 @@</span><br><span> #include <arch/io.h></span><br><span> #include <console/console.h></span><br><span> #include <delay.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <halt.h></span><br><span> #include <string.h></span><br><span> #include "me.h"</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c</span><br><span>index 4c67aea..3cd98ac 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/early_smbus.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/early_smbus.c</span><br><span>@@ -16,7 +16,6 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <southbridge/intel/common/smbus.h></span><br><span> #include "pch.h"</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/early_spi.c b/src/southbridge/intel/lynxpoint/early_spi.c</span><br><span>index 1400837..e3f07ad 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/early_spi.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/early_spi.c</span><br><span>@@ -16,7 +16,6 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <delay.h></span><br><span> #include "pch.h"</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c</span><br><span>index 60ab09d..4b44716 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/early_usb.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/early_usb.c</span><br><span>@@ -15,7 +15,6 @@</span><br><span> */</span><br><span> </span><br><span> #include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span> #include "pch.h"</span><br><span> </span><br><span>diff --git a/src/southbridge/ti/pci7420/cardbus.c b/src/southbridge/ti/pci7420/cardbus.c</span><br><span>index 910b0c8..3c88529 100644</span><br><span>--- a/src/southbridge/ti/pci7420/cardbus.c</span><br><span>+++ b/src/southbridge/ti/pci7420/cardbus.c</span><br><span>@@ -18,7 +18,6 @@</span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <device/pci_ops.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <console/console.h></span><br><span> #include <device/cardbus.h></span><br><span> #include "pci7420.h"</span><br><span>diff --git a/src/southbridge/ti/pci7420/firewire.c b/src/southbridge/ti/pci7420/firewire.c</span><br><span>index e42b6a6..1379d59 100644</span><br><span>--- a/src/southbridge/ti/pci7420/firewire.c</span><br><span>+++ b/src/southbridge/ti/pci7420/firewire.c</span><br><span>@@ -18,7 +18,6 @@</span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <device/pci_ops.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <console/console.h></span><br><span> #include <device/cardbus.h></span><br><span> #include "pci7420.h"</span><br><span>diff --git a/src/southbridge/ti/pcixx12/pcixx12.c b/src/southbridge/ti/pcixx12/pcixx12.c</span><br><span>index ab7231e..6385ba9 100644</span><br><span>--- a/src/southbridge/ti/pcixx12/pcixx12.c</span><br><span>+++ b/src/southbridge/ti/pcixx12/pcixx12.c</span><br><span>@@ -17,7 +17,6 @@</span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <device/pci_ops.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span> #include <console/console.h></span><br><span> #include <device/cardbus.h></span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30120">change 30120</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30120"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ia640131479d4221ccd84613033f28de3932b8bff </div>
<div style="display:none"> Gerrit-Change-Number: 30120 </div>
<div style="display:none"> Gerrit-PatchSet: 5 </div>
<div style="display:none"> Gerrit-Owner: HAOUAS Elyes <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: Alexander Couzens <lynxis@fe80.eu> </div>
<div style="display:none"> Gerrit-Reviewer: Damien Zammit <damien@zamaudio.com> </div>
<div style="display:none"> Gerrit-Reviewer: David Guckian <david.guckian@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: HAOUAS Elyes <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: Huang Jin <huang.jin@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Michał Żygowski <michal.zygowski@3mdeb.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>
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<div style="display:none"> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Werner Zeh <werner.zeh@siemens.com> </div>
<div style="display:none"> Gerrit-Reviewer: York Yang <york.yang@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>