[coreboot-gerrit] Change in ...coreboot[master]: [WIP] Enable FIT support on RISC-V

Tue Dec 18 15:23:10 CET 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30292 )

Change subject: [WIP] Enable FIT support on RISC-V
......................................................................

Patch Set 1:

(76 comments)

https://review.coreboot.org/#/c/30292/1/spike.dts 
File spike.dts:

https://review.coreboot.org/#/c/30292/1/spike.dts@16 
PS1, Line 16:     compatible = "ucbbar,spike-bare-dev";
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https://review.coreboot.org/#/c/30292/1/spike.dts@17 
PS1, Line 17:     model = "ucbbar,spike-bare";
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https://review.coreboot.org/#/c/30292/1/spike.dts@18 
PS1, Line 18:     cpus {
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https://review.coreboot.org/#/c/30292/1/spike.dts@19 
PS1, Line 19:         #address-cells = <0x00000001>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@20 
PS1, Line 20:         #size-cells = <0x00000000>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@21 
PS1, Line 21:         timebase-frequency = <10000000>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@21 
PS1, Line 21:         timebase-frequency = <10000000>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@22 
PS1, Line 22:         cpu at 0 {
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https://review.coreboot.org/#/c/30292/1/spike.dts@22 
PS1, Line 22:         cpu at 0 {
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https://review.coreboot.org/#/c/30292/1/spike.dts@23 
PS1, Line 23:             device_type = "cpu";
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https://review.coreboot.org/#/c/30292/1/spike.dts@23 
PS1, Line 23:             device_type = "cpu";
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https://review.coreboot.org/#/c/30292/1/spike.dts@24 
PS1, Line 24:             reg = <0x00000000>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@24 
PS1, Line 24:             reg = <0x00000000>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@25 
PS1, Line 25:             status = "okay";
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https://review.coreboot.org/#/c/30292/1/spike.dts@25 
PS1, Line 25:             status = "okay";
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https://review.coreboot.org/#/c/30292/1/spike.dts@26 
PS1, Line 26:             compatible = "riscv";
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https://review.coreboot.org/#/c/30292/1/spike.dts@26 
PS1, Line 26:             compatible = "riscv";
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https://review.coreboot.org/#/c/30292/1/spike.dts@27 
PS1, Line 27:             riscv,isa = "rv64imafdc";
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https://review.coreboot.org/#/c/30292/1/spike.dts@27 
PS1, Line 27:             riscv,isa = "rv64imafdc";
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https://review.coreboot.org/#/c/30292/1/spike.dts@28 
PS1, Line 28:             mmu-type = "riscv,sv48";
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https://review.coreboot.org/#/c/30292/1/spike.dts@28 
PS1, Line 28:             mmu-type = "riscv,sv48";
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https://review.coreboot.org/#/c/30292/1/spike.dts@29 
PS1, Line 29:             clock-frequency = <1000000000>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@29 
PS1, Line 29:             clock-frequency = <1000000000>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@30 
PS1, Line 30:             interrupt-controller {
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https://review.coreboot.org/#/c/30292/1/spike.dts@30 
PS1, Line 30:             interrupt-controller {
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https://review.coreboot.org/#/c/30292/1/spike.dts@31 
PS1, Line 31:                 #interrupt-cells = <0x00000001>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@32 
PS1, Line 32:                 interrupt-controller;
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https://review.coreboot.org/#/c/30292/1/spike.dts@32 
PS1, Line 32:                 interrupt-controller;
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https://review.coreboot.org/#/c/30292/1/spike.dts@33 
PS1, Line 33:                 compatible = "riscv,cpu-intc";
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https://review.coreboot.org/#/c/30292/1/spike.dts@33 
PS1, Line 33:                 compatible = "riscv,cpu-intc";
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https://review.coreboot.org/#/c/30292/1/spike.dts@34 
PS1, Line 34:                 linux,phandle = <0x00000001>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@34 
PS1, Line 34:                 linux,phandle = <0x00000001>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@35 
PS1, Line 35:                 phandle = <0x00000001>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@35 
PS1, Line 35:                 phandle = <0x00000001>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@36 
PS1, Line 36:             };
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https://review.coreboot.org/#/c/30292/1/spike.dts@36 
PS1, Line 36:             };
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https://review.coreboot.org/#/c/30292/1/spike.dts@37 
PS1, Line 37:         };
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https://review.coreboot.org/#/c/30292/1/spike.dts@37 
PS1, Line 37:         };
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https://review.coreboot.org/#/c/30292/1/spike.dts@38 
PS1, Line 38:     };
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https://review.coreboot.org/#/c/30292/1/spike.dts@39 
PS1, Line 39:     memory at 80000000 {
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https://review.coreboot.org/#/c/30292/1/spike.dts@40 
PS1, Line 40:         device_type = "memory";
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https://review.coreboot.org/#/c/30292/1/spike.dts@40 
PS1, Line 40:         device_type = "memory";
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https://review.coreboot.org/#/c/30292/1/spike.dts@41 
PS1, Line 41:         reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@41 
PS1, Line 41:         reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@42 
PS1, Line 42:     };
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https://review.coreboot.org/#/c/30292/1/spike.dts@43 
PS1, Line 43:     soc {
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https://review.coreboot.org/#/c/30292/1/spike.dts@44 
PS1, Line 44:         #address-cells = <0x00000002>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@45 
PS1, Line 45:         #size-cells = <0x00000002>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@46 
PS1, Line 46:         compatible = "ucbbar,spike-bare-soc", "simple-bus";
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https://review.coreboot.org/#/c/30292/1/spike.dts@46 
PS1, Line 46:         compatible = "ucbbar,spike-bare-soc", "simple-bus";
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https://review.coreboot.org/#/c/30292/1/spike.dts@47 
PS1, Line 47:         ranges;
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https://review.coreboot.org/#/c/30292/1/spike.dts@47 
PS1, Line 47:         ranges;
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https://review.coreboot.org/#/c/30292/1/spike.dts@48 
PS1, Line 48:         clint at 2000000 {
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https://review.coreboot.org/#/c/30292/1/spike.dts@48 
PS1, Line 48:         clint at 2000000 {
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https://review.coreboot.org/#/c/30292/1/spike.dts@49 
PS1, Line 49:             compatible = "riscv,clint0";
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https://review.coreboot.org/#/c/30292/1/spike.dts@49 
PS1, Line 49:             compatible = "riscv,clint0";
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https://review.coreboot.org/#/c/30292/1/spike.dts@50 
PS1, Line 50:             interrupts-extended = <0x00000001 0x00000003 0x00000001 0x00000007>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@50 
PS1, Line 50:             interrupts-extended = <0x00000001 0x00000003 0x00000001 0x00000007>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@51 
PS1, Line 51:             reg = <0x00000000 0x02000000 0x00000000 0x000c0000>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@51 
PS1, Line 51:             reg = <0x00000000 0x02000000 0x00000000 0x000c0000>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@52 
PS1, Line 52:         };
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https://review.coreboot.org/#/c/30292/1/spike.dts@52 
PS1, Line 52:         };
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https://review.coreboot.org/#/c/30292/1/spike.dts@53 
PS1, Line 53:         uart at 2100000 {
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https://review.coreboot.org/#/c/30292/1/spike.dts@53 
PS1, Line 53:         uart at 2100000 {
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https://review.coreboot.org/#/c/30292/1/spike.dts@54 
PS1, Line 54:             compatible = "serial";
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https://review.coreboot.org/#/c/30292/1/spike.dts@54 
PS1, Line 54:             compatible = "serial";
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https://review.coreboot.org/#/c/30292/1/spike.dts@55 
PS1, Line 55:             reg = <0x00000000 0x02100000 0x00000000 0x00000008>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@55 
PS1, Line 55:             reg = <0x00000000 0x02100000 0x00000000 0x00000008>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@56 
PS1, Line 56:             reg-shift = <0x00000000>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@56 
PS1, Line 56:             reg-shift = <0x00000000>;
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https://review.coreboot.org/#/c/30292/1/spike.dts@57 
PS1, Line 57:         };
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https://review.coreboot.org/#/c/30292/1/spike.dts@57 
PS1, Line 57:         };
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https://review.coreboot.org/#/c/30292/1/spike.dts@58 
PS1, Line 58:     };
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https://review.coreboot.org/#/c/30292/1/src/arch/riscv/boot.c 
File src/arch/riscv/boot.c:

https://review.coreboot.org/#/c/30292/1/src/arch/riscv/boot.c@45 
PS1, Line 45: 			 * FIXME: This is wrong and will crash. Linux can't (in early
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https://review.coreboot.org/#/c/30292/1/src/arch/riscv/boot.c@46 
PS1, Line 46: 			 * boot) access memory that's before its own loading address.
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https://review.coreboot.org/#/c/30292/1/src/arch/riscv/boot.c@47 
PS1, Line 47: 			 * We need to copy the FDT to a place where Linux can access it.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5ebc6cc2cc9e328f36d70fba13555386bb8c29d6
Gerrit-Change-Number: 30292
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Philipp Hug <philipp at hug.cx>
Gerrit-Reviewer: ron minnich <rminnich at gmail.com>
Gerrit-CC: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Tue, 18 Dec 2018 14:23:10 +0000
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