[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/common: Remove common chip config use_fsp_mp_init
Subrata Banik (Code Review)
gerrit at coreboot.org
Tue Dec 18 10:31:22 CET 2018
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30289
Change subject: soc/intel/common: Remove common chip config use_fsp_mp_init
......................................................................
soc/intel/common: Remove common chip config use_fsp_mp_init
This patch ensures to make use of CONFIG_USE_INTEL_FSP_MP_INIT
Kconfig to peform MP initialization by either coreboot or FSP.
Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
M src/mainboard/intel/saddlebrook/devicetree.cb
M src/soc/intel/apollolake/chip.c
M src/soc/intel/cannonlake/romstage/fsp_params.c
M src/soc/intel/common/block/chip/chip.c
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/include/intelblocks/chip.h
M src/soc/intel/common/block/include/intelblocks/mp_init.h
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip_fsp20.c
12 files changed, 35 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/30289/1
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
index df09b42..257ad1d 100644
--- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
@@ -152,7 +152,6 @@
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
- .use_fsp_mp_init = CONFIG_USE_INTEL_FSP_MP_INIT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
index f86e45c..0d2ea76 100644
--- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
+++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
@@ -176,7 +176,6 @@
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
- .use_fsp_mp_init = CONFIG_USE_INTEL_FSP_MP_INIT,
.gspi[1] = {
.speed_mhz = 1,
.early_init = 1,
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
index 7b42bcf..62c7a82 100644
--- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
+++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
@@ -176,7 +176,6 @@
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
- .use_fsp_mp_init = CONFIG_USE_INTEL_FSP_MP_INIT,
.gspi[1] = {
.speed_mhz = 1,
.early_init = 1,
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 8b71c9f..cd9db48 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -142,11 +142,6 @@
.voltage_limit = 0x5F0 \
}"
- # Skip coreboot MP Init
- register "common_soc_config" = "{
- .use_fsp_mp_init = CONFIG_USE_INTEL_FSP_MP_INIT,
- }"
-
# Enable x1 slot
register "PcieRpEnable[7]" = "1"
register "PcieRpClkReqSupport[7]" = "1"
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 1c8f321..da44249 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -35,6 +35,7 @@
#include <fsp/util.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/itss.h>
+#include <intelblocks/mp_init.h>
#include <intelblocks/pmclib.h>
#include <romstage_handoff.h>
#include <soc/cpu.h>
@@ -647,7 +648,7 @@
if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK))
silconfig->MonitorMwaitEnable = 0;
- silconfig->SkipMpInit = !chip_get_fsp_mp_init();
+ silconfig->SkipMpInit = !is_fsp_mp_init_enable();
/* Disable setting of EISS bit in FSP. */
silconfig->SpiEiss = 0;
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 8f6fa2f..ef2afdb 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -17,6 +17,7 @@
#include <chip.h>
#include <console/console.h>
#include <fsp/util.h>
+#include <intelblocks/mp_init.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
@@ -54,7 +55,7 @@
else
m_cfg->VmxEnable = config->VmxEnable;
#if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE)
- m_cfg->SkipMpInit = !chip_get_fsp_mp_init();
+ m_cfg->SkipMpInit = !is_fsp_mp_init_enable();
#endif
/* If ISH is enabled, enable ISH elements */
if (!dev)
diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c
index aecf060..cfec4ec 100644
--- a/src/soc/intel/common/block/chip/chip.c
+++ b/src/soc/intel/common/block/chip/chip.c
@@ -32,18 +32,3 @@
return soc_config;
}
-
-/*
- * This function will get MP Init config
- *
- * Return values:
- * 0 = Make use of coreboot MP Init
- * 1 = Make use of FSP MP Init
- */
-int chip_get_fsp_mp_init(void)
-{
- const struct soc_intel_common_config *common_config;
- common_config = chip_get_common_soc_structure();
-
- return common_config->use_fsp_mp_init;
-}
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index b4a6eb2..00fe659 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -140,12 +140,28 @@
return false;
}
+/*
+ * This function will get MP Init config
+ *
+ * Mainboard user to decide if platform need to implement
+ * FSP MP Init by selecting CONFIG_USE_INTEL_FSP_MP_INIT
+ * Kconfig
+ *
+ * Return values:
+ * 0 = Make use of coreboot MP Init
+ * 1 = Make use of FSP MP Init
+ */
+int is_fsp_mp_init_enable(void)
+{
+ return CONFIG_USE_INTEL_FSP_MP_INIT;
+}
+
static void init_cpus(void *unused)
{
struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
assert(dev != NULL);
- if (chip_get_fsp_mp_init() && !is_mp_service_ppi_enable())
+ if (is_fsp_mp_init_enable() && !is_mp_service_ppi_enable())
return;
microcode_patch = intel_microcode_find();
@@ -163,7 +179,7 @@
/* Ensure to re-program all MTRRs based on DRAM resource settings */
static void post_cpus_init(void *unused)
{
- if (chip_get_fsp_mp_init() && !is_mp_service_ppi_enable())
+ if (is_fsp_mp_init_enable() && !is_mp_service_ppi_enable())
return;
if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL, 1000) < 0)
diff --git a/src/soc/intel/common/block/include/intelblocks/chip.h b/src/soc/intel/common/block/include/intelblocks/chip.h
index d761f6b..555bdaa 100644
--- a/src/soc/intel/common/block/include/intelblocks/chip.h
+++ b/src/soc/intel/common/block/include/intelblocks/chip.h
@@ -33,24 +33,9 @@
int chipset_lockdown;
struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX];
- /*
- * Option for mainboard to skip coreboot MP initialization
- * 0 = Make use of coreboot MP Init
- * 1 = Make use of FSP MP Init
- */
- uint8_t use_fsp_mp_init;
};
/* This function to retrieve soc config structure required by common code */
const struct soc_intel_common_config *chip_get_common_soc_structure(void);
-/*
- * This function will get MP Init config
- *
- * Return values:
- * 0 = Make use of coreboot MP Init
- * 1 = Make use of FSP MP Init
- */
-int chip_get_fsp_mp_init(void);
-
#endif /* SOC_INTEL_COMMON_BLOCK_CHIP_H */
diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h
index 841295e..c95b1af 100644
--- a/src/soc/intel/common/block/include/intelblocks/mp_init.h
+++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h
@@ -99,4 +99,13 @@
*/
bool is_mp_service_ppi_enable(void);
+/*
+ * This function will get FSP MP Init status
+ *
+ * Return values:
+ * 0 = Make use of coreboot MP Init
+ * 1 = Make use of FSP MP Init
+ */
+int is_fsp_mp_init_enable(void);
+
#endif /* SOC_INTEL_COMMON_BLOCK_MP_INIT_H */
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index fb01183..4bd00a4 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -22,6 +22,7 @@
#include <fsp/util.h>
#include <intelblocks/chip.h>
#include <intelblocks/itss.h>
+#include <intelblocks/mp_init.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <soc/acpi.h>
@@ -194,7 +195,7 @@
params->SerialIrqConfigStartFramePulse =
config->SerialIrqConfigStartFramePulse;
- params->SkipMpInit = !chip_get_fsp_mp_init();
+ params->SkipMpInit = !is_fsp_mp_init_enable();
for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++)
params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 18c2aef..d07c97b 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -26,6 +26,7 @@
#include <fsp/util.h>
#include <intelblocks/chip.h>
#include <intelblocks/itss.h>
+#include <intelblocks/mp_init.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <romstage_handoff.h>
@@ -419,7 +420,7 @@
params->PchSirqEnable = config->SerialIrqConfigSirqEnable;
params->PchSirqMode = config->SerialIrqConfigSirqMode;
- params->CpuConfig.Bits.SkipMpInit = !chip_get_fsp_mp_init();
+ params->CpuConfig.Bits.SkipMpInit = !is_fsp_mp_init_enable();
for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++)
params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
--
To view, visit https://review.coreboot.org/c/coreboot/+/30289
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280
Gerrit-Change-Number: 30289
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
Gerrit-MessageType: newchange
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