<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30289">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common: Remove common chip config use_fsp_mp_init<br><br>This patch ensures to make use of CONFIG_USE_INTEL_FSP_MP_INIT<br>Kconfig to peform MP initialization by either coreboot or FSP.<br><br>Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb<br>M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb<br>M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb<br>M src/mainboard/intel/saddlebrook/devicetree.cb<br>M src/soc/intel/apollolake/chip.c<br>M src/soc/intel/cannonlake/romstage/fsp_params.c<br>M src/soc/intel/common/block/chip/chip.c<br>M src/soc/intel/common/block/cpu/mp_init.c<br>M src/soc/intel/common/block/include/intelblocks/chip.h<br>M src/soc/intel/common/block/include/intelblocks/mp_init.h<br>M src/soc/intel/skylake/chip.c<br>M src/soc/intel/skylake/chip_fsp20.c<br>12 files changed, 35 insertions(+), 44 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/30289/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb</span><br><span>index df09b42..257ad1d 100644</span><br><span>--- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb</span><br><span>@@ -152,7 +152,6 @@</span><br><span> </span><br><span> register "common_soc_config" = "{</span><br><span> .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,</span><br><span style="color: hsl(0, 100%, 40%);">- .use_fsp_mp_init = CONFIG_USE_INTEL_FSP_MP_INIT,</span><br><span> .gspi[0] = {</span><br><span> .speed_mhz = 1,</span><br><span> .early_init = 1,</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb</span><br><span>index f86e45c..0d2ea76 100644</span><br><span>--- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb</span><br><span>@@ -176,7 +176,6 @@</span><br><span> </span><br><span> register "common_soc_config" = "{</span><br><span> .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,</span><br><span style="color: hsl(0, 100%, 40%);">- .use_fsp_mp_init = CONFIG_USE_INTEL_FSP_MP_INIT,</span><br><span> .gspi[1] = {</span><br><span> .speed_mhz = 1,</span><br><span> .early_init = 1,</span><br><span>diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb</span><br><span>index 7b42bcf..62c7a82 100644</span><br><span>--- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb</span><br><span>@@ -176,7 +176,6 @@</span><br><span> </span><br><span> register "common_soc_config" = "{</span><br><span> .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,</span><br><span style="color: hsl(0, 100%, 40%);">- .use_fsp_mp_init = CONFIG_USE_INTEL_FSP_MP_INIT,</span><br><span> .gspi[1] = {</span><br><span> .speed_mhz = 1,</span><br><span> .early_init = 1,</span><br><span>diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb</span><br><span>index 8b71c9f..cd9db48 100644</span><br><span>--- a/src/mainboard/intel/saddlebrook/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/saddlebrook/devicetree.cb</span><br><span>@@ -142,11 +142,6 @@</span><br><span> .voltage_limit = 0x5F0 \</span><br><span> }"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- # Skip coreboot MP Init</span><br><span style="color: hsl(0, 100%, 40%);">- register "common_soc_config" = "{</span><br><span style="color: hsl(0, 100%, 40%);">- .use_fsp_mp_init = CONFIG_USE_INTEL_FSP_MP_INIT,</span><br><span style="color: hsl(0, 100%, 40%);">- }"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> # Enable x1 slot</span><br><span> register "PcieRpEnable[7]" = "1"</span><br><span> register "PcieRpClkReqSupport[7]" = "1"</span><br><span>diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c</span><br><span>index 1c8f321..da44249 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.c</span><br><span>+++ b/src/soc/intel/apollolake/chip.c</span><br><span>@@ -35,6 +35,7 @@</span><br><span> #include <fsp/util.h></span><br><span> #include <intelblocks/cpulib.h></span><br><span> #include <intelblocks/itss.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/mp_init.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span> #include <romstage_handoff.h></span><br><span> #include <soc/cpu.h></span><br><span>@@ -647,7 +648,7 @@</span><br><span> if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK))</span><br><span> silconfig->MonitorMwaitEnable = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- silconfig->SkipMpInit = !chip_get_fsp_mp_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ silconfig->SkipMpInit = !is_fsp_mp_init_enable();</span><br><span> </span><br><span> /* Disable setting of EISS bit in FSP. */</span><br><span> silconfig->SpiEiss = 0;</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c</span><br><span>index 8f6fa2f..ef2afdb 100644</span><br><span>--- a/src/soc/intel/cannonlake/romstage/fsp_params.c</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c</span><br><span>@@ -17,6 +17,7 @@</span><br><span> #include <chip.h></span><br><span> #include <console/console.h></span><br><span> #include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/mp_init.h></span><br><span> #include <soc/iomap.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/romstage.h></span><br><span>@@ -54,7 +55,7 @@</span><br><span> else</span><br><span> m_cfg->VmxEnable = config->VmxEnable;</span><br><span> #if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE)</span><br><span style="color: hsl(0, 100%, 40%);">- m_cfg->SkipMpInit = !chip_get_fsp_mp_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->SkipMpInit = !is_fsp_mp_init_enable();</span><br><span> #endif</span><br><span> /* If ISH is enabled, enable ISH elements */</span><br><span> if (!dev)</span><br><span>diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c</span><br><span>index aecf060..cfec4ec 100644</span><br><span>--- a/src/soc/intel/common/block/chip/chip.c</span><br><span>+++ b/src/soc/intel/common/block/chip/chip.c</span><br><span>@@ -32,18 +32,3 @@</span><br><span> </span><br><span> return soc_config;</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This function will get MP Init config</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Return values:</span><br><span style="color: hsl(0, 100%, 40%);">- * 0 = Make use of coreboot MP Init</span><br><span style="color: hsl(0, 100%, 40%);">- * 1 = Make use of FSP MP Init</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-int chip_get_fsp_mp_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- const struct soc_intel_common_config *common_config;</span><br><span style="color: hsl(0, 100%, 40%);">- common_config = chip_get_common_soc_structure();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return common_config->use_fsp_mp_init;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c</span><br><span>index b4a6eb2..00fe659 100644</span><br><span>--- a/src/soc/intel/common/block/cpu/mp_init.c</span><br><span>+++ b/src/soc/intel/common/block/cpu/mp_init.c</span><br><span>@@ -140,12 +140,28 @@</span><br><span> return false;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This function will get MP Init config</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Mainboard user to decide if platform need to implement</span><br><span style="color: hsl(120, 100%, 40%);">+ * FSP MP Init by selecting CONFIG_USE_INTEL_FSP_MP_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+ * Kconfig</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Return values:</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Make use of coreboot MP Init</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Make use of FSP MP Init</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+int is_fsp_mp_init_enable(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return CONFIG_USE_INTEL_FSP_MP_INIT;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void init_cpus(void *unused)</span><br><span> {</span><br><span> struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);</span><br><span> assert(dev != NULL);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (chip_get_fsp_mp_init() && !is_mp_service_ppi_enable())</span><br><span style="color: hsl(120, 100%, 40%);">+ if (is_fsp_mp_init_enable() && !is_mp_service_ppi_enable())</span><br><span> return;</span><br><span> </span><br><span> microcode_patch = intel_microcode_find();</span><br><span>@@ -163,7 +179,7 @@</span><br><span> /* Ensure to re-program all MTRRs based on DRAM resource settings */</span><br><span> static void post_cpus_init(void *unused)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- if (chip_get_fsp_mp_init() && !is_mp_service_ppi_enable())</span><br><span style="color: hsl(120, 100%, 40%);">+ if (is_fsp_mp_init_enable() && !is_mp_service_ppi_enable())</span><br><span> return;</span><br><span> </span><br><span> if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL, 1000) < 0)</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/chip.h b/src/soc/intel/common/block/include/intelblocks/chip.h</span><br><span>index d761f6b..555bdaa 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/chip.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/chip.h</span><br><span>@@ -33,24 +33,9 @@</span><br><span> int chipset_lockdown;</span><br><span> struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];</span><br><span> struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX];</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Option for mainboard to skip coreboot MP initialization</span><br><span style="color: hsl(0, 100%, 40%);">- * 0 = Make use of coreboot MP Init</span><br><span style="color: hsl(0, 100%, 40%);">- * 1 = Make use of FSP MP Init</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t use_fsp_mp_init;</span><br><span> };</span><br><span> </span><br><span> /* This function to retrieve soc config structure required by common code */</span><br><span> const struct soc_intel_common_config *chip_get_common_soc_structure(void);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This function will get MP Init config</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Return values:</span><br><span style="color: hsl(0, 100%, 40%);">- * 0 = Make use of coreboot MP Init</span><br><span style="color: hsl(0, 100%, 40%);">- * 1 = Make use of FSP MP Init</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-int chip_get_fsp_mp_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #endif /* SOC_INTEL_COMMON_BLOCK_CHIP_H */</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h</span><br><span>index 841295e..c95b1af 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/mp_init.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h</span><br><span>@@ -99,4 +99,13 @@</span><br><span> */</span><br><span> bool is_mp_service_ppi_enable(void);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This function will get FSP MP Init status</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Return values:</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Make use of coreboot MP Init</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Make use of FSP MP Init</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+int is_fsp_mp_init_enable(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #endif /* SOC_INTEL_COMMON_BLOCK_MP_INIT_H */</span><br><span>diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c</span><br><span>index fb01183..4bd00a4 100644</span><br><span>--- a/src/soc/intel/skylake/chip.c</span><br><span>+++ b/src/soc/intel/skylake/chip.c</span><br><span>@@ -22,6 +22,7 @@</span><br><span> #include <fsp/util.h></span><br><span> #include <intelblocks/chip.h></span><br><span> #include <intelblocks/itss.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/mp_init.h></span><br><span> #include <intelblocks/xdci.h></span><br><span> #include <intelpch/lockdown.h></span><br><span> #include <soc/acpi.h></span><br><span>@@ -194,7 +195,7 @@</span><br><span> params->SerialIrqConfigStartFramePulse =</span><br><span> config->SerialIrqConfigStartFramePulse;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- params->SkipMpInit = !chip_get_fsp_mp_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ params->SkipMpInit = !is_fsp_mp_init_enable();</span><br><span> </span><br><span> for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++)</span><br><span> params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];</span><br><span>diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>index 18c2aef..d07c97b 100644</span><br><span>--- a/src/soc/intel/skylake/chip_fsp20.c</span><br><span>+++ b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>@@ -26,6 +26,7 @@</span><br><span> #include <fsp/util.h></span><br><span> #include <intelblocks/chip.h></span><br><span> #include <intelblocks/itss.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/mp_init.h></span><br><span> #include <intelblocks/xdci.h></span><br><span> #include <intelpch/lockdown.h></span><br><span> #include <romstage_handoff.h></span><br><span>@@ -419,7 +420,7 @@</span><br><span> params->PchSirqEnable = config->SerialIrqConfigSirqEnable;</span><br><span> params->PchSirqMode = config->SerialIrqConfigSirqMode;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- params->CpuConfig.Bits.SkipMpInit = !chip_get_fsp_mp_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ params->CpuConfig.Bits.SkipMpInit = !is_fsp_mp_init_enable();</span><br><span> </span><br><span> for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++)</span><br><span> params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30289">change 30289</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30289"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280 </div>
<div style="display:none"> Gerrit-Change-Number: 30289 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>