[coreboot-gerrit] Change in ...coreboot[master]: mb/google/hatch: Add SoC and EC asl files in DSDT

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30282


Change subject: mb/google/hatch: Add SoC and EC asl files in DSDT
......................................................................

mb/google/hatch: Add SoC and EC asl files in DSDT

Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/hatch/dsdt.asl
M src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
3 files changed, 39 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/30282/1

diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 7af3e43..19230f7 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -11,7 +11,6 @@
 	select HATCH_USE_SPI_TPM
 	select MAINBOARD_HAS_CHROMEOS
 	select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
-	select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK
 	select SOC_INTEL_COFFEELAKE
 	select SYSTEM_TYPE_LAPTOP
 
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl
index cb83509..02e4779 100644
--- a/src/mainboard/google/hatch/dsdt.asl
+++ b/src/mainboard/google/hatch/dsdt.asl
@@ -14,6 +14,9 @@
  */
 
 #include <arch/acpi.h>
+#include "variant/ec.h"
+#include "variant/gpio.h"
+
 DefinitionBlock(
 	"dsdt.aml",
 	"DSDT",
@@ -23,4 +26,37 @@
 	0x20110725	/* OEM revision */
 )
 {
+	// Some generic macros
+	#include <soc/intel/cannonlake/acpi/platform.asl>
+
+	// global NVS and variables
+	#include <soc/intel/cannonlake/acpi/globalnvs.asl>
+
+	// CPU
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/cannonlake/acpi/northbridge.asl>
+			#include <soc/intel/cannonlake/acpi/southbridge.asl>
+		}
+	}
+
+	#if IS_ENABLED(CONFIG_CHROMEOS)
+	// Chrome OS specific
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+	#endif
+
+	// Chipset specific sleep states
+	#include <soc/intel/cannonlake/acpi/sleepstates.asl>
+
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
 }
diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
index e537a93..3878029 100644
--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
@@ -28,4 +28,7 @@
 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
 #define GPE_EC_WAKE		GPE0_LAN_WAK
 
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI		GPE0_ESPI
+
 #endif /* BASEBOARD_GPIO_H */

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6
Gerrit-Change-Number: 30282
Gerrit-PatchSet: 1
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-MessageType: newchange
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