<p>Aamir Bohra has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30282">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/hatch: Add SoC and EC asl files in DSDT<br><br>Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6<br>Signed-off-by: Aamir Bohra <aamir.bohra@intel.com><br>---<br>M src/mainboard/google/hatch/Kconfig<br>M src/mainboard/google/hatch/dsdt.asl<br>M src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h<br>3 files changed, 39 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/30282/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig</span><br><span>index 7af3e43..19230f7 100644</span><br><span>--- a/src/mainboard/google/hatch/Kconfig</span><br><span>+++ b/src/mainboard/google/hatch/Kconfig</span><br><span>@@ -11,7 +11,6 @@</span><br><span> select HATCH_USE_SPI_TPM</span><br><span> select MAINBOARD_HAS_CHROMEOS</span><br><span> select SOC_INTEL_CANNONLAKE_MEMCFG_INIT</span><br><span style="color: hsl(0, 100%, 40%);">- select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK</span><br><span> select SOC_INTEL_COFFEELAKE</span><br><span> select SYSTEM_TYPE_LAPTOP</span><br><span> </span><br><span>diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl</span><br><span>index cb83509..02e4779 100644</span><br><span>--- a/src/mainboard/google/hatch/dsdt.asl</span><br><span>+++ b/src/mainboard/google/hatch/dsdt.asl</span><br><span>@@ -14,6 +14,9 @@</span><br><span> */</span><br><span> </span><br><span> #include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "variant/ec.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "variant/gpio.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> DefinitionBlock(</span><br><span> "dsdt.aml",</span><br><span> "DSDT",</span><br><span>@@ -23,4 +26,37 @@</span><br><span> 0x20110725 /* OEM revision */</span><br><span> )</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ // Some generic macros</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/cannonlake/acpi/platform.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // global NVS and variables</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/cannonlake/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <cpu/intel/common/acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/cannonlake/acpi/northbridge.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/cannonlake/acpi/southbridge.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #if IS_ENABLED(CONFIG_CHROMEOS)</span><br><span style="color: hsl(120, 100%, 40%);">+ // Chrome OS specific</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <vendorcode/google/chromeos/acpi/chromeos.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Chipset specific sleep states</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/cannonlake/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Chrome OS Embedded Controller */</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB.PCI0.LPCB)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ACPI code for EC SuperIO functions */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <ec/google/chromeec/acpi/superio.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ /* ACPI code for EC functions */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <ec/google/chromeec/acpi/ec.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h</span><br><span>index e537a93..3878029 100644</span><br><span>--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h</span><br><span>+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h</span><br><span>@@ -28,4 +28,7 @@</span><br><span> /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */</span><br><span> #define GPE_EC_WAKE GPE0_LAN_WAK</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* eSPI virtual wire reporting */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_SCI_GPI GPE0_ESPI</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #endif /* BASEBOARD_GPIO_H */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30282">change 30282</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6 </div>
<div style="display:none"> Gerrit-Change-Number: 30282 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>