[coreboot-gerrit] Change in ...coreboot[master]: mb/google/hatch: Add memory init setup for hatch
Aamir Bohra (Code Review)
gerrit at coreboot.org
Sun Dec 16 09:07:15 CET 2018
Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30248
Change subject: mb/google/hatch: Add memory init setup for hatch
......................................................................
mb/google/hatch: Add memory init setup for hatch
This implemetation adds below support:
1. Add support to read memory strap.
2. Add support to configure below memory parameters
-> rcomp resistor configuration
-> dqs mapping
-> ect and ca vref config
3. Include SPD configuration
Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/hatch/Makefile.inc
M src/mainboard/google/hatch/romstage.c
A src/mainboard/google/hatch/spd/Makefile.inc
A src/mainboard/google/hatch/spd/empty_ddr4.spd.hex
M src/mainboard/google/hatch/variants/baseboard/Makefile.inc
M src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/hatch/variants/baseboard/memory.c
9 files changed, 150 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/30248/1
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 9dbefed..7af3e43 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -6,7 +6,6 @@
select DRIVERS_I2C_HID
select DRIVERS_SPI_ACPI
select EC_GOOGLE_CHROMEEC
- select GENERIC_SPD_BIN
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HATCH_USE_SPI_TPM
@@ -14,7 +13,6 @@
select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK
select SOC_INTEL_COFFEELAKE
- select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP
if BOARD_GOOGLE_BASEBOARD_HATCH
diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc
index 54e4281..ca8c7f2 100644
--- a/src/mainboard/google/hatch/Makefile.inc
+++ b/src/mainboard/google/hatch/Makefile.inc
@@ -31,3 +31,5 @@
VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+
+subdirs-y += spd
diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c
index b79feb8..401f41f 100644
--- a/src/mainboard/google/hatch/romstage.c
+++ b/src/mainboard/google/hatch/romstage.c
@@ -13,8 +13,17 @@
* GNU General Public License for more details.
*/
+#include <baseboard/variants.h>
+#include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
+ const struct spd_info spd = {
+ .spd_by_index = true,
+ .spd_spec.spd_index = variant_memory_sku(),
+ };
+
+ cannonlake_memcfg_init(&memupd->FspmConfig,
+ variant_memory_params(), &spd);
}
diff --git a/src/mainboard/google/hatch/spd/Makefile.inc b/src/mainboard/google/hatch/spd/Makefile.inc
new file mode 100644
index 0000000..e18306c
--- /dev/null
+++ b/src/mainboard/google/hatch/spd/Makefile.inc
@@ -0,0 +1,36 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+SPD_SOURCES = empty_ddr4 # 0b000
+
+ifeq ($(SPD_SOURCES),)
+ SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this)
+else
+ SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+endif
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/hatch/spd/empty_ddr4.spd.hex b/src/mainboard/google/hatch/spd/empty_ddr4.spd.hex
new file mode 100644
index 0000000..67b46cd
--- /dev/null
+++ b/src/mainboard/google/hatch/spd/empty_ddr4.spd.hex
@@ -0,0 +1,32 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc
index dffacbb..8de1d4f 100644
--- a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc
+++ b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc
@@ -1,6 +1,7 @@
bootblock-y += gpio.c
romstage-y += gpio.c
+romstage-y += memory.c
ramstage-y += gpio.c
diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
index c9f8b4c..7940cff 100644
--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
@@ -18,4 +18,10 @@
#include <soc/gpio.h>
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0 GPP_F20
+#define GPIO_MEM_CONFIG_1 GPP_F21
+#define GPIO_MEM_CONFIG_2 GPP_F11
+#define GPIO_MEM_CONFIG_3 GPP_F22
+
#endif /* BASEBOARD_GPIO_H */
diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
index 90a52c0..f40b239 100644
--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
@@ -26,7 +26,10 @@
const struct pad_config *variant_early_gpio_table(size_t *num);
/* Return memory SKU for the board. */
-size_t variant_memory_sku(void);
+int variant_memory_sku(void);
+
+/* Return board specific memory configuration */
+const struct cnl_mb_cfg *__weak variant_memory_params(void);
/* Return ChromeOS gpio table and fill in number of entries. */
const struct cros_gpio *variant_cros_gpios(size_t *num);
diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c
new file mode 100644
index 0000000..1ef64ed
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/baseboard/memory.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <baseboard/gpio.h>
+#include <gpio.h>
+#include <soc/cnl_memcfg_init.h>
+
+static const struct cnl_mb_cfg baseboard_memcfg = {
+ /*
+ * The dqs_map arrays map the ddr4 pins to the SoC pins
+ * for both channels.
+ *
+ * the index = pin number on ddr4 part
+ * the value = pin number on SoC
+ */
+ .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 },
+ .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 },
+
+ /* Baseboard uses 120, 81 and 100 rcomp resistors */
+ .rcomp_resistor = { 120, 81, 100 },
+
+ /* Baseboard Rcomp target values */
+ .rcomp_targets = { 100, 40, 20, 20, 26 },
+
+ /* Set CaVref config to 2 */
+ .vref_ca_config = 2,
+
+ /* Enable Early Command Training */
+ .ect = 1,
+};
+
+const struct cnl_mb_cfg *__weak variant_memory_params(void)
+{
+ return &baseboard_memcfg;
+}
+
+int __weak variant_memory_sku(void)
+{
+ gpio_t spd_gpios[] = {
+ GPIO_MEM_CONFIG_0,
+ GPIO_MEM_CONFIG_1,
+ GPIO_MEM_CONFIG_2,
+ GPIO_MEM_CONFIG_3,
+ };
+
+ return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19
Gerrit-Change-Number: 30248
Gerrit-PatchSet: 1
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-MessageType: newchange
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