<p>Aamir Bohra has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30248">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/hatch: Add memory init setup for hatch<br><br>This implemetation adds below support:<br><br>1. Add support to read memory strap.<br>2. Add support to configure below memory parameters<br> -> rcomp resistor configuration<br> -> dqs mapping<br> -> ect and ca vref config<br>3. Include SPD configuration<br><br>Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19<br>Signed-off-by: Aamir Bohra <aamir.bohra@intel.com><br>---<br>M src/mainboard/google/hatch/Kconfig<br>M src/mainboard/google/hatch/Makefile.inc<br>M src/mainboard/google/hatch/romstage.c<br>A src/mainboard/google/hatch/spd/Makefile.inc<br>A src/mainboard/google/hatch/spd/empty_ddr4.spd.hex<br>M src/mainboard/google/hatch/variants/baseboard/Makefile.inc<br>M src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h<br>M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h<br>A src/mainboard/google/hatch/variants/baseboard/memory.c<br>9 files changed, 150 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/30248/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig</span><br><span>index 9dbefed..7af3e43 100644</span><br><span>--- a/src/mainboard/google/hatch/Kconfig</span><br><span>+++ b/src/mainboard/google/hatch/Kconfig</span><br><span>@@ -6,7 +6,6 @@</span><br><span> select DRIVERS_I2C_HID</span><br><span> select DRIVERS_SPI_ACPI</span><br><span> select EC_GOOGLE_CHROMEEC</span><br><span style="color: hsl(0, 100%, 40%);">- select GENERIC_SPD_BIN</span><br><span> select HAVE_ACPI_RESUME</span><br><span> select HAVE_ACPI_TABLES</span><br><span> select HATCH_USE_SPI_TPM</span><br><span>@@ -14,7 +13,6 @@</span><br><span> select SOC_INTEL_CANNONLAKE_MEMCFG_INIT</span><br><span> select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK</span><br><span> select SOC_INTEL_COFFEELAKE</span><br><span style="color: hsl(0, 100%, 40%);">- select SPD_READ_BY_WORD</span><br><span> select SYSTEM_TYPE_LAPTOP</span><br><span> </span><br><span> if BOARD_GOOGLE_BASEBOARD_HATCH</span><br><span>diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc</span><br><span>index 54e4281..ca8c7f2 100644</span><br><span>--- a/src/mainboard/google/hatch/Makefile.inc</span><br><span>+++ b/src/mainboard/google/hatch/Makefile.inc</span><br><span>@@ -31,3 +31,5 @@</span><br><span> VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))</span><br><span> subdirs-y += variants/$(VARIANT_DIR)</span><br><span> CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += spd</span><br><span>diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c</span><br><span>index b79feb8..401f41f 100644</span><br><span>--- a/src/mainboard/google/hatch/romstage.c</span><br><span>+++ b/src/mainboard/google/hatch/romstage.c</span><br><span>@@ -13,8 +13,17 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/cnl_memcfg_init.h></span><br><span> #include <soc/romstage.h></span><br><span> </span><br><span> void mainboard_memory_init_params(FSPM_UPD *memupd)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct spd_info spd = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .spd_by_index = true,</span><br><span style="color: hsl(120, 100%, 40%);">+ .spd_spec.spd_index = variant_memory_sku(),</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cannonlake_memcfg_init(&memupd->FspmConfig,</span><br><span style="color: hsl(120, 100%, 40%);">+ variant_memory_params(), &spd);</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/hatch/spd/Makefile.inc b/src/mainboard/google/hatch/spd/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..e18306c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/hatch/spd/Makefile.inc</span><br><span>@@ -0,0 +1,36 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_BIN = $(obj)/spd.bin</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES = empty_ddr4 # 0b000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ifeq ($(SPD_SOURCES),)</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this)</span><br><span style="color: hsl(120, 100%, 40%);">+else</span><br><span style="color: hsl(120, 100%, 40%);">+ SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# Include spd ROM data</span><br><span style="color: hsl(120, 100%, 40%);">+$(SPD_BIN): $(SPD_DEPS)</span><br><span style="color: hsl(120, 100%, 40%);">+ for f in $+; \</span><br><span style="color: hsl(120, 100%, 40%);">+ do for c in $$(cat $$f | grep -v ^#); \</span><br><span style="color: hsl(120, 100%, 40%);">+ do printf $$(printf '\%o' 0x$$c); \</span><br><span style="color: hsl(120, 100%, 40%);">+ done; \</span><br><span style="color: hsl(120, 100%, 40%);">+ done > $@</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+cbfs-files-y += spd.bin</span><br><span style="color: hsl(120, 100%, 40%);">+spd.bin-file := $(SPD_BIN)</span><br><span style="color: hsl(120, 100%, 40%);">+spd.bin-type := spd</span><br><span>diff --git a/src/mainboard/google/hatch/spd/empty_ddr4.spd.hex b/src/mainboard/google/hatch/spd/empty_ddr4.spd.hex</span><br><span>new file mode 100644</span><br><span>index 0000000..67b46cd</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/hatch/spd/empty_ddr4.spd.hex</span><br><span>@@ -0,0 +1,32 @@</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc</span><br><span>index dffacbb..8de1d4f 100644</span><br><span>--- a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc</span><br><span>+++ b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc</span><br><span>@@ -1,6 +1,7 @@</span><br><span> bootblock-y += gpio.c</span><br><span> </span><br><span> romstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += memory.c</span><br><span> </span><br><span> ramstage-y += gpio.c</span><br><span> </span><br><span>diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h</span><br><span>index c9f8b4c..7940cff 100644</span><br><span>--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h</span><br><span>+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h</span><br><span>@@ -18,4 +18,10 @@</span><br><span> </span><br><span> #include <soc/gpio.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Memory configuration board straps */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_0 GPP_F20</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_1 GPP_F21</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_2 GPP_F11</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_3 GPP_F22</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #endif /* BASEBOARD_GPIO_H */</span><br><span>diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h</span><br><span>index 90a52c0..f40b239 100644</span><br><span>--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h</span><br><span>+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h</span><br><span>@@ -26,7 +26,10 @@</span><br><span> const struct pad_config *variant_early_gpio_table(size_t *num);</span><br><span> </span><br><span> /* Return memory SKU for the board. */</span><br><span style="color: hsl(0, 100%, 40%);">-size_t variant_memory_sku(void);</span><br><span style="color: hsl(120, 100%, 40%);">+int variant_memory_sku(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Return board specific memory configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+const struct cnl_mb_cfg *__weak variant_memory_params(void);</span><br><span> </span><br><span> /* Return ChromeOS gpio table and fill in number of entries. */</span><br><span> const struct cros_gpio *variant_cros_gpios(size_t *num);</span><br><span>diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c</span><br><span>new file mode 100644</span><br><span>index 0000000..1ef64ed</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/hatch/variants/baseboard/memory.c</span><br><span>@@ -0,0 +1,60 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/cnl_memcfg_init.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct cnl_mb_cfg baseboard_memcfg = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The dqs_map arrays map the ddr4 pins to the SoC pins</span><br><span style="color: hsl(120, 100%, 40%);">+ * for both channels.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * the index = pin number on ddr4 part</span><br><span style="color: hsl(120, 100%, 40%);">+ * the value = pin number on SoC</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 },</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Baseboard uses 120, 81 and 100 rcomp resistors */</span><br><span style="color: hsl(120, 100%, 40%);">+ .rcomp_resistor = { 120, 81, 100 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Baseboard Rcomp target values */</span><br><span style="color: hsl(120, 100%, 40%);">+ .rcomp_targets = { 100, 40, 20, 20, 26 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set CaVref config to 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ .vref_ca_config = 2,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable Early Command Training */</span><br><span style="color: hsl(120, 100%, 40%);">+ .ect = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct cnl_mb_cfg *__weak variant_memory_params(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return &baseboard_memcfg;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int __weak variant_memory_sku(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_t spd_gpios[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_MEM_CONFIG_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_MEM_CONFIG_1,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_MEM_CONFIG_2,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_MEM_CONFIG_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30248">change 30248</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30248"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19 </div>
<div style="display:none"> Gerrit-Change-Number: 30248 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>