[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/broadwell: implement RMRR ACPI table

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30234 )

Change subject: soc/intel/broadwell: implement RMRR ACPI table
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Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/30234/1/src/soc/intel/broadwell/Kconfig 
File src/soc/intel/broadwell/Kconfig:

https://review.coreboot.org/#/c/30234/1/src/soc/intel/broadwell/Kconfig@39 
PS1, Line 39: SOC_INTEL_COMMON_BLOCK
if you are intended to make use of intel common code, then you should break ur CL into 2 part.

1. make use of Intel common code in BDW context
2. Make use of those SA code to create your ASL

but in #1, you have bigger problem because from design standpoint, we have agreed to add support from Intel Gen 6 onwards (skylake) platform but BDW is older generation platform. where we haven't validated those socs.

once you decided to make use of that, you have further 2 challenges 

1. Add support in gen 4 and gen 5 platform 
2. remove redundant code, once you have included SA kconfig, entire library code will be there, you are having duplicate functions now hence you might need to remove those duplicate code from soc



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1a10a4f91b787b72f33150031b783d426148c25d
Gerrit-Change-Number: 30234
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier at gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h at gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Sat, 15 Dec 2018 16:19:18 +0000
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