[coreboot-gerrit] Change in ...coreboot[master]: amd/stoneyridge: Add calls to code to reset eMMC
Richard Spiegel (Code Review)
gerrit at coreboot.org
Sat Dec 15 02:49:35 CET 2018
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30237
Change subject: amd/stoneyridge: Add calls to code to reset eMMC
......................................................................
amd/stoneyridge: Add calls to code to reset eMMC
Create devicetree to define the bridge used for the eMMC controller, than
add calls to program the bridge and execute the eMMC reset. Also add code
to read back eMMC base address and verify reset completion
BUG=b:118680303
TEST=Added debug code to analyze the effects. Build and boot grunt.
Change-Id: Ic664a4d7936c441fe920e30b89c2ea4452df401b
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/mainboard/google/kahlee/Kconfig
M src/mainboard/google/kahlee/variants/grunt/devicetree.cb
M src/soc/amd/stoneyridge/chip.h
M src/soc/amd/stoneyridge/finalize.c
M src/soc/amd/stoneyridge/romstage.c
5 files changed, 89 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/30237/1
diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig
index 97d15f5..cd1bffa 100644
--- a/src/mainboard/google/kahlee/Kconfig
+++ b/src/mainboard/google/kahlee/Kconfig
@@ -45,6 +45,8 @@
select PCIEXP_L1_SUB_STATE
select HAVE_EM100_SUPPORT
select SYSTEM_TYPE_LAPTOP
+ select DRIVERS_TEMP_BRIDGE
+ select DRIVERS_EMMC_RESET
if BOARD_GOOGLE_BASEBOARD_KAHLEE
diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb
index b37e1bf..e830e72 100644
--- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb
@@ -23,6 +23,7 @@
register "stapm_percent" = "80"
register "stapm_time_ms" = "2500000"
register "stapm_power_mw" = "7800"
+ register "emmc_bridge_function" = "4"
# Enable I2C0 for audio, USB3 hub at 400kHz
register "i2c[0]" = "{
diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h
index 92223d1..a6416ba 100644
--- a/src/soc/amd/stoneyridge/chip.h
+++ b/src/soc/amd/stoneyridge/chip.h
@@ -72,6 +72,8 @@
*/
u8 lvds_poseq_varybl_to_blon;
u8 lvds_poseq_blon_to_varybl;
+ /* Provide the function of the GPP bridge supporting the eMMC chip. */
+ u8 emmc_bridge_function;
};
typedef struct soc_amd_stoneyridge_config config_t;
diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c
index 45e6595..5a0a430 100644
--- a/src/soc/amd/stoneyridge/finalize.c
+++ b/src/soc/amd/stoneyridge/finalize.c
@@ -19,6 +19,10 @@
#include <bootstate.h>
#include <timer.h>
#include <console/console.h>
+#include <device/temp_bridge.h>
+#include <device/emmc.h>
+#include <chip.h>
+#include <soc/pci_devs.h>
static void per_core_finalize(void *unused)
{
@@ -49,9 +53,47 @@
printk(BIOS_WARNING, "Failed to finalize all cores\n");
}
+static void emmc(void)
+{
+ const struct soc_amd_stoneyridge_config *cfg;
+ const struct device *dev = dev_find_slot(0, GNB_DEVFN);
+ struct device_addresses params;
+ uint8_t *bh720;
+ struct device *bridge;
+ int status;
+ uint8_t function;
+
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n");
+ return;
+ }
+
+ if (IS_ENABLED(CONFIG_DRIVERS_TEMP_BRIDGE) &&
+ IS_ENABLED(CONFIG_DRIVERS_EMMC_RESET)) {
+ cfg = dev->chip_info;
+ function = cfg->emmc_bridge_function;
+ bridge = _SOC_DEV(2, function);
+
+ params.used[0] = MEMORY_ADDRESS;
+ params.used[1] = NOT_USED;
+ params.used[2] = NOT_USED;
+ params.used[3] = NOT_USED;
+ params.used[4] = NOT_USED;
+ params.used[5] = NOT_USED;
+ params.memory_range = 0;
+ status = get_bases(bridge, ¶ms);
+ bh720 = (uint8_t *)params.bases[0];
+ status = emmc_check_reset(bh720);
+ if (status != EMMC_STATUS_SUCCESS)
+ printk(BIOS_SPEW, "ERROR: emmc_check_reset returned"
+ " %d\n", status);
+ }
+}
+
static void soc_finalize(void *unused)
{
finalize_cores();
+ emmc();
post_code(POST_OS_BOOT);
}
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 9314488..5658fcc 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -34,6 +34,8 @@
#include <soc/romstage.h>
#include <soc/southbridge.h>
#include <amdblocks/psp.h>
+#include <device/temp_bridge.h>
+#include <device/emmc.h>
void __weak mainboard_romstage_entry(int s3_resume)
{
@@ -78,6 +80,44 @@
agesa_call();
}
+static void start_emmc_reset(void)
+{
+ const struct soc_amd_stoneyridge_config *cfg;
+ const struct device *dev = dev_find_slot(0, GNB_DEVFN);
+ struct device_addresses params;
+ uint8_t *bh720;
+ int status;
+ pci_devfn_t bridge;
+ uint8_t function;
+
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n");
+ return;
+ }
+
+ if (IS_ENABLED(CONFIG_DRIVERS_TEMP_BRIDGE) &&
+ IS_ENABLED(CONFIG_DRIVERS_EMMC_RESET)) {
+ cfg = dev->chip_info;
+ function = cfg->emmc_bridge_function;
+ bridge = _SOC_DEV(2, function);
+ params.used[0] = MEMORY_ADDRESS;
+ params.used[1] = NOT_USED;
+ params.used[2] = NOT_USED;
+ params.used[3] = NOT_USED;
+ params.used[4] = NOT_USED;
+ params.used[5] = NOT_USED;
+ params.memory_range = 0;
+ status = set_bases(bridge, ¶ms);
+ if (status != TP_BRIDGE_SUCCESS)
+ return;
+ bh720 = (uint8_t *)params.bases[0];
+ status = emmc_start_reset(bh720);
+ if (status != EMMC_STATUS_SUCCESS)
+ printk(BIOS_SPEW, "ERROR: emmc_start_reset returned"
+ " %d\n", status);
+ release_bases(bridge);
+ }
+}
asmlinkage void car_stage_entry(void)
{
struct postcar_frame pcf;
@@ -164,6 +204,8 @@
postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB,
MTRR_TYPE_WRBACK);
+ if (!s3_resume)
+ start_emmc_reset();
/* Cache the memory-mapped boot media. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
--
To view, visit https://review.coreboot.org/c/coreboot/+/30237
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic664a4d7936c441fe920e30b89c2ea4452df401b
Gerrit-Change-Number: 30237
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
Gerrit-MessageType: newchange
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