<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30237">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Add calls to code to reset eMMC<br><br>Create devicetree to define the bridge used for the eMMC controller, than<br>add calls to program the bridge and execute the eMMC reset. Also add code<br>to read back eMMC base address and verify reset completion<br><br>BUG=b:118680303<br>TEST=Added debug code to analyze the effects. Build and boot grunt.<br><br>Change-Id: Ic664a4d7936c441fe920e30b89c2ea4452df401b<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/mainboard/google/kahlee/Kconfig<br>M src/mainboard/google/kahlee/variants/grunt/devicetree.cb<br>M src/soc/amd/stoneyridge/chip.h<br>M src/soc/amd/stoneyridge/finalize.c<br>M src/soc/amd/stoneyridge/romstage.c<br>5 files changed, 89 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/30237/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig</span><br><span>index 97d15f5..cd1bffa 100644</span><br><span>--- a/src/mainboard/google/kahlee/Kconfig</span><br><span>+++ b/src/mainboard/google/kahlee/Kconfig</span><br><span>@@ -45,6 +45,8 @@</span><br><span> select PCIEXP_L1_SUB_STATE</span><br><span> select HAVE_EM100_SUPPORT</span><br><span> select SYSTEM_TYPE_LAPTOP</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_TEMP_BRIDGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_EMMC_RESET</span><br><span> </span><br><span> if BOARD_GOOGLE_BASEBOARD_KAHLEE</span><br><span> </span><br><span>diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb</span><br><span>index b37e1bf..e830e72 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb</span><br><span>+++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb</span><br><span>@@ -23,6 +23,7 @@</span><br><span> register "stapm_percent" = "80"</span><br><span> register "stapm_time_ms" = "2500000"</span><br><span> register "stapm_power_mw" = "7800"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_bridge_function" = "4"</span><br><span> </span><br><span> # Enable I2C0 for audio, USB3 hub at 400kHz</span><br><span> register "i2c[0]" = "{</span><br><span>diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h</span><br><span>index 92223d1..a6416ba 100644</span><br><span>--- a/src/soc/amd/stoneyridge/chip.h</span><br><span>+++ b/src/soc/amd/stoneyridge/chip.h</span><br><span>@@ -72,6 +72,8 @@</span><br><span> */</span><br><span> u8 lvds_poseq_varybl_to_blon;</span><br><span> u8 lvds_poseq_blon_to_varybl;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Provide the function of the GPP bridge supporting the eMMC chip. */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 emmc_bridge_function;</span><br><span> };</span><br><span> </span><br><span> typedef struct soc_amd_stoneyridge_config config_t;</span><br><span>diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c</span><br><span>index 45e6595..5a0a430 100644</span><br><span>--- a/src/soc/amd/stoneyridge/finalize.c</span><br><span>+++ b/src/soc/amd/stoneyridge/finalize.c</span><br><span>@@ -19,6 +19,10 @@</span><br><span> #include <bootstate.h></span><br><span> #include <timer.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/temp_bridge.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/emmc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span> </span><br><span> static void per_core_finalize(void *unused)</span><br><span> {</span><br><span>@@ -49,9 +53,47 @@</span><br><span> printk(BIOS_WARNING, "Failed to finalize all cores\n");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void emmc(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_amd_stoneyridge_config *cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct device *dev = dev_find_slot(0, GNB_DEVFN);</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device_addresses params;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t *bh720;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *bridge;</span><br><span style="color: hsl(120, 100%, 40%);">+ int status;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t function;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev || !dev->chip_info) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_DRIVERS_TEMP_BRIDGE) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ IS_ENABLED(CONFIG_DRIVERS_EMMC_RESET)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ function = cfg->emmc_bridge_function;</span><br><span style="color: hsl(120, 100%, 40%);">+ bridge = _SOC_DEV(2, function);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ params.used[0] = MEMORY_ADDRESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ params.used[1] = NOT_USED;</span><br><span style="color: hsl(120, 100%, 40%);">+ params.used[2] = NOT_USED;</span><br><span style="color: hsl(120, 100%, 40%);">+ params.used[3] = NOT_USED;</span><br><span style="color: hsl(120, 100%, 40%);">+ params.used[4] = NOT_USED;</span><br><span style="color: hsl(120, 100%, 40%);">+ params.used[5] = NOT_USED;</span><br><span style="color: hsl(120, 100%, 40%);">+ params.memory_range = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ status = get_bases(bridge, ¶ms);</span><br><span style="color: hsl(120, 100%, 40%);">+ bh720 = (uint8_t *)params.bases[0];</span><br><span style="color: hsl(120, 100%, 40%);">+ status = emmc_check_reset(bh720);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (status != EMMC_STATUS_SUCCESS)</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "ERROR: emmc_check_reset returned"</span><br><span style="color: hsl(120, 100%, 40%);">+ " %d\n", status);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void soc_finalize(void *unused)</span><br><span> {</span><br><span> finalize_cores();</span><br><span style="color: hsl(120, 100%, 40%);">+ emmc();</span><br><span> </span><br><span> post_code(POST_OS_BOOT);</span><br><span> }</span><br><span>diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c</span><br><span>index 9314488..5658fcc 100644</span><br><span>--- a/src/soc/amd/stoneyridge/romstage.c</span><br><span>+++ b/src/soc/amd/stoneyridge/romstage.c</span><br><span>@@ -34,6 +34,8 @@</span><br><span> #include <soc/romstage.h></span><br><span> #include <soc/southbridge.h></span><br><span> #include <amdblocks/psp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/temp_bridge.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/emmc.h></span><br><span> </span><br><span> void __weak mainboard_romstage_entry(int s3_resume)</span><br><span> {</span><br><span>@@ -78,6 +80,44 @@</span><br><span> agesa_call();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void start_emmc_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_amd_stoneyridge_config *cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct device *dev = dev_find_slot(0, GNB_DEVFN);</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device_addresses params;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t *bh720;</span><br><span style="color: hsl(120, 100%, 40%);">+ int status;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t bridge;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t function;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev || !dev->chip_info) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_DRIVERS_TEMP_BRIDGE) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ IS_ENABLED(CONFIG_DRIVERS_EMMC_RESET)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ function = cfg->emmc_bridge_function;</span><br><span style="color: hsl(120, 100%, 40%);">+ bridge = _SOC_DEV(2, function);</span><br><span style="color: hsl(120, 100%, 40%);">+ params.used[0] = MEMORY_ADDRESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ params.used[1] = NOT_USED;</span><br><span style="color: hsl(120, 100%, 40%);">+ params.used[2] = NOT_USED;</span><br><span style="color: hsl(120, 100%, 40%);">+ params.used[3] = NOT_USED;</span><br><span style="color: hsl(120, 100%, 40%);">+ params.used[4] = NOT_USED;</span><br><span style="color: hsl(120, 100%, 40%);">+ params.used[5] = NOT_USED;</span><br><span style="color: hsl(120, 100%, 40%);">+ params.memory_range = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ status = set_bases(bridge, ¶ms);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (status != TP_BRIDGE_SUCCESS)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ bh720 = (uint8_t *)params.bases[0];</span><br><span style="color: hsl(120, 100%, 40%);">+ status = emmc_start_reset(bh720);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (status != EMMC_STATUS_SUCCESS)</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "ERROR: emmc_start_reset returned"</span><br><span style="color: hsl(120, 100%, 40%);">+ " %d\n", status);</span><br><span style="color: hsl(120, 100%, 40%);">+ release_bases(bridge);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span> asmlinkage void car_stage_entry(void)</span><br><span> {</span><br><span> struct postcar_frame pcf;</span><br><span>@@ -164,6 +204,8 @@</span><br><span> postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB,</span><br><span> MTRR_TYPE_WRBACK);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ if (!s3_resume)</span><br><span style="color: hsl(120, 100%, 40%);">+ start_emmc_reset();</span><br><span> /* Cache the memory-mapped boot media. */</span><br><span> postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30237">change 30237</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30237"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ic664a4d7936c441fe920e30b89c2ea4452df401b </div>
<div style="display:none"> Gerrit-Change-Number: 30237 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>