[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/broadwell: implement RMRR ACPI table

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30234


Change subject: soc/intel/broadwell: implement RMRR ACPI table
......................................................................

soc/intel/broadwell: implement RMRR ACPI table

Modeled after Skylake implementation; use intel common SA
functions to get RMRR addresses

Test: build/boot google/samus, observe IOMMU fully functional
with intel_iommu=on kernel parameter

Change-Id: I1a10a4f91b787b72f33150031b783d426148c25d
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/acpi.c
M src/soc/intel/broadwell/include/soc/systemagent.h
3 files changed, 14 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30234/1

diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index e6cbd95..e9ec036 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -36,6 +36,8 @@
 	select UDELAY_TSC
 	select SOC_INTEL_COMMON
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
+	select SOC_INTEL_COMMON_BLOCK
+	select SOC_INTEL_COMMON_BLOCK_SA
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select HAVE_SPI_CONSOLE_SUPPORT
 	select CPU_INTEL_COMMON
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index 9c6bd9b..5a30d66 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -29,6 +29,7 @@
 #include <cpu/x86/tsc.h>
 #include <cpu/intel/turbo.h>
 #include <ec/google/chromeec/ec.h>
+#include <intelblocks/systemagent.h>
 #include <vendorcode/google/chromeos/gnvs.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
@@ -590,12 +591,20 @@
 	/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
 	if (igfx_dev && igfx_dev->enabled && gfxvtbar
 			&& gfxvten && !MCHBAR32(GFXVTBAR + 4)) {
-		const unsigned long tmp = current;
+		unsigned long tmp = current;
 
 		current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
 		current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
 
 		acpi_dmar_drhd_fixup(tmp, current);
+
+		/* Add RMRR entry */
+		tmp = current;
+
+		current += acpi_create_dmar_rmrr(current, 0,
+				sa_get_gsm_base(), sa_get_tolud_base() - 1);
+		current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
+		acpi_dmar_rmrr_fixup(tmp, current);
 	}
 
 	/* VTVC0BAR has to be set, enabled, and in 32-bit space */
diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h
index 92e79cc..72601fc 100644
--- a/src/soc/intel/broadwell/include/soc/systemagent.h
+++ b/src/soc/intel/broadwell/include/soc/systemagent.h
@@ -94,9 +94,11 @@
 
 /* MCHBAR */
 
+#ifndef MCHBAR32
 #define MCHBAR8(x)	*((volatile u8 *)(MCH_BASE_ADDRESS + x))
 #define MCHBAR16(x)	*((volatile u16 *)(MCH_BASE_ADDRESS + x))
 #define MCHBAR32(x)	*((volatile u32 *)(MCH_BASE_ADDRESS + x))
+#endif
 
 #define MCHBAR_PEI_VERSION	0x5034
 #define BIOS_RESET_CPL		0x5da8

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1a10a4f91b787b72f33150031b783d426148c25d
Gerrit-Change-Number: 30234
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
Gerrit-MessageType: newchange
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